On Thu, Mar 13, 2014 at 01:40:28AM +0000, Damien Lespiau wrote:
> While wandering in the spec, I noticed that BDW removes those 2 bits
> from INSTPM. I couldn't find any direct way to invalidate the TLB (ie
> without the ring working already). Maybe someone will be more lucky.
>
> At least, we now know we may be a problem.
>
> Signed-off-by: Damien Lespiau <damien.lesp...@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ringbuffer.c | 10 ++++++++--
> 1 file changed, 8 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c
> b/drivers/gpu/drm/i915/intel_ringbuffer.c
> index c50388a..4eb3e06 100644
> --- a/drivers/gpu/drm/i915/intel_ringbuffer.c
> +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
> @@ -981,8 +981,14 @@ void intel_ring_setup_status_page(struct
> intel_ring_buffer *ring)
> I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
> POSTING_READ(mmio);
>
> - /* Flush the TLB for this page */
> - if (INTEL_INFO(dev)->gen >= 6) {
> + /*
> + * Flush the TLB for this page
> + *
> + * FIXME: These two bits have disappeared on gen8, so a question
> + * arises: do we still need this and if so how should we go about
> + * invalidating the TLB?
> + */
> + if (INTEL_INFO(dev)->gen >= 6 && INTEL_INFO(dev)->gen < 8) {
> u32 reg = RING_INSTPM(ring->mmio_base);
>
> /* ring should be idle before issuing a sync flush*/
I'm missing something on the original patch,
884020bf3d2a3787a1cc6df902e98e0eec60330b. How were we emitting
breadcrumbs without flushing the TLB? All bathcbuffers should be
bookended by a TLB invalidate already, so I'm not sure the logic holds.
Chris could explain that one a bit further?
The only reason I bring this up is I'd like to rip this out completely
and have Thiago retest, or at least change the comment/commit message to
be to reflect whatever light Chris sheds on the matter.
Anyway, the bits are definitely gone, and I also can't find a non-ring
based replacement.
Reviewed-by: Ben Widawsky <b...@bwidawsk.net>
--
Ben Widawsky, Intel Open Source Technology Center
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