> -----Original Message-----
> From: Jani Nikula <[email protected]>
> Sent: Wednesday, October 9, 2024 3:30 PM
> To: Kandpal, Suraj <[email protected]>; intel-
> [email protected]; [email protected]
> Cc: Nautiyal, Ankit K <[email protected]>; Kandpal, Suraj
> <[email protected]>
> Subject: Re: [PATCH] drm/i915/dp_mst: Fix dsc mst bw overhead calculation
>
> On Wed, 09 Oct 2024, Suraj Kandpal <[email protected]> wrote:
> > Fix the DSC flag assignment based on the dsc_slice_count returned to
> > avoid divide by zero error.
> >
> > Fixes: 4e0837a8d00a ("drm/i915/dp_mst: Account for FEC and DSC
> > overhead during BW allocation")
> > Signed-off-by: Suraj Kandpal <[email protected]>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 7 ++++++-
> > 1 file changed, 6 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index 4765bda154c1..bacd294d6bb6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -105,11 +105,16 @@ static int intel_dp_mst_bw_overhead(const
> struct intel_crtc_state *crtc_state,
> > if (dsc) {
> > int num_joined_pipes =
> intel_crtc_num_joined_pipes(crtc_state);
> >
> > - flags |= DRM_DP_BW_OVERHEAD_DSC;
> > dsc_slice_count = intel_dp_dsc_get_slice_count(connector,
> > adjusted_mode-
> >clock,
> > adjusted_mode-
> >hdisplay,
> >
> num_joined_pipes);
> > + /*
> > + * Try with dsc only if dsc_slice_count has a sane value i.e
> value is no
> > + * 0
> > + */
> > + if (dsc_slice_count)
> > + flags |= DRM_DP_BW_OVERHEAD_DSC;
>
> Do you think that's enough to handle the error?!
Well this will make sure that if dsc_slice_count ends up being zero we don't
take dsc overhead into account.
Which should be enough to make sure we don't go and end up having a divide by
zero error
Regards,
Suraj Kandpal
>
> BR,
> Jani.
>
> > }
> >
> > overhead = drm_dp_bw_overhead(crtc_state->lane_count,
>
> --
> Jani Nikula, Intel
