On Wed, 09 Oct 2024, Ville Syrjala <[email protected]> wrote: > From: Ville Syrjälä <[email protected]> > > We've determined that accessing the (supposedly) 16bit > interrupt registers on gen2 as 32bit works just fine. > We already dropped the special case from the main interrupt > code, do so also for the gt interrupt stuff. > > Signed-off-by: Ville Syrjälä <[email protected]>
Reviewed-by: Jani Nikula <[email protected]> > --- > drivers/gpu/drm/i915/gt/gen2_engine_cs.c | 17 ----------------- > drivers/gpu/drm/i915/gt/gen2_engine_cs.h | 2 -- > drivers/gpu/drm/i915/gt/intel_ring_submission.c | 5 +---- > 3 files changed, 1 insertion(+), 23 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > index 8fe0499308ff..54077cab8e16 100644 > --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.c > @@ -290,23 +290,6 @@ int gen4_emit_bb_start(struct i915_request *rq, > return 0; > } > > -void gen2_irq_enable(struct intel_engine_cs *engine) > -{ > - struct drm_i915_private *i915 = engine->i915; > - > - i915->irq_mask &= ~engine->irq_enable_mask; > - intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask); > - ENGINE_POSTING_READ16(engine, RING_IMR); > -} > - > -void gen2_irq_disable(struct intel_engine_cs *engine) > -{ > - struct drm_i915_private *i915 = engine->i915; > - > - i915->irq_mask |= engine->irq_enable_mask; > - intel_uncore_write16(&i915->uncore, GEN2_IMR, i915->irq_mask); > -} > - > void gen3_irq_enable(struct intel_engine_cs *engine) > { > engine->i915->irq_mask &= ~engine->irq_enable_mask; > diff --git a/drivers/gpu/drm/i915/gt/gen2_engine_cs.h > b/drivers/gpu/drm/i915/gt/gen2_engine_cs.h > index a5cd64a65c9e..2f707620b3d4 100644 > --- a/drivers/gpu/drm/i915/gt/gen2_engine_cs.h > +++ b/drivers/gpu/drm/i915/gt/gen2_engine_cs.h > @@ -28,8 +28,6 @@ int gen4_emit_bb_start(struct i915_request *rq, > u64 offset, u32 length, > unsigned int dispatch_flags); > > -void gen2_irq_enable(struct intel_engine_cs *engine); > -void gen2_irq_disable(struct intel_engine_cs *engine); > void gen3_irq_enable(struct intel_engine_cs *engine); > void gen3_irq_disable(struct intel_engine_cs *engine); > void gen5_irq_enable(struct intel_engine_cs *engine); > diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c > b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > index 72277bc8322e..694cb79d5452 100644 > --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c > +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c > @@ -1090,12 +1090,9 @@ static void setup_irq(struct intel_engine_cs *engine) > } else if (GRAPHICS_VER(i915) >= 5) { > engine->irq_enable = gen5_irq_enable; > engine->irq_disable = gen5_irq_disable; > - } else if (GRAPHICS_VER(i915) >= 3) { > + } else { > engine->irq_enable = gen3_irq_enable; > engine->irq_disable = gen3_irq_disable; > - } else { > - engine->irq_enable = gen2_irq_enable; > - engine->irq_disable = gen2_irq_disable; > } > } -- Jani Nikula, Intel
