There is unnecessary complexity in frontbuffer tracking invalidate and flush callbacks. Simplify them a bit with some minor changes to sequences:
Invalidate: 1. Additionally write single full frame bit when selective fetch is enabled. This should be ok as continuous full frame bit is already set. 2. Rewrite bits in PSR2_MAN_TRK_CTL if two invalidate calls in row without flush in between (psr.psr2_sel_fetch_cff_enabled == true). Flush: 1. intel_dp->psr.psr2_sel_fetch_cff_enabled is clearn also when it is already false. Signed-off-by: Jouni Högander <[email protected]> --- drivers/gpu/drm/i915/display/intel_psr.c | 66 +++++------------------- 1 file changed, 12 insertions(+), 54 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index b32020321ca7a..5be8076475f0b 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -3069,28 +3069,8 @@ static void intel_psr_work(struct work_struct *work) static void _psr_invalidate_handle(struct intel_dp *intel_dp) { - struct intel_display *display = to_intel_display(intel_dp); - enum transcoder cpu_transcoder = intel_dp->psr.transcoder; - if (intel_dp->psr.psr2_sel_fetch_enabled) { - u32 val; - - if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { - /* Send one update otherwise lag is observed in screen */ - intel_de_write(display, - CURSURFLIVE(display, intel_dp->psr.pipe), - 0); - return; - } - - val = man_trk_ctl_enable_bit_get(display) | - man_trk_ctl_partial_frame_bit_get(display) | - man_trk_ctl_continuos_full_frame(display); - intel_de_write(display, - PSR2_MAN_TRK_CTL(display, cpu_transcoder), - val); - intel_de_write(display, - CURSURFLIVE(display, intel_dp->psr.pipe), 0); + psr_force_exit(intel_dp); intel_dp->psr.psr2_sel_fetch_cff_enabled = true; } else { intel_psr_exit(intel_dp); @@ -3172,43 +3152,21 @@ static void _psr_flush_handle(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); struct drm_i915_private *dev_priv = to_i915(display->drm); - enum transcoder cpu_transcoder = intel_dp->psr.transcoder; + + psr_force_exit(intel_dp); if (intel_dp->psr.psr2_sel_fetch_enabled) { - if (intel_dp->psr.psr2_sel_fetch_cff_enabled) { - /* can we turn CFF off? */ - if (intel_dp->psr.busy_frontbuffer_bits == 0) { - u32 val = man_trk_ctl_enable_bit_get(display) | - man_trk_ctl_partial_frame_bit_get(display) | - man_trk_ctl_single_full_frame_bit_get(display) | - man_trk_ctl_continuos_full_frame(display); - - /* - * Set psr2_sel_fetch_cff_enabled as false to allow selective - * updates. Still keep cff bit enabled as we don't have proper - * SU configuration in case update is sent for any reason after - * sff bit gets cleared by the HW on next vblank. - */ - intel_de_write(display, - PSR2_MAN_TRK_CTL(display, cpu_transcoder), - val); - intel_de_write(display, - CURSURFLIVE(display, intel_dp->psr.pipe), - 0); - intel_dp->psr.psr2_sel_fetch_cff_enabled = false; - } - } else { + /* can we turn CFF off? */ + if (intel_dp->psr.busy_frontbuffer_bits == 0) /* - * continuous full frame is disabled, only a single full - * frame is required + * Set psr2_sel_fetch_cff_enabled as false to allow selective + * updates. Still keep cff bit enabled as we don't have proper + * SU configuration in case update is sent for any reason after + * sff bit gets cleared by the HW on next vblank. */ - psr_force_exit(intel_dp); - } - } else { - psr_force_exit(intel_dp); - - if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) - queue_work(dev_priv->unordered_wq, &intel_dp->psr.work); + intel_dp->psr.psr2_sel_fetch_cff_enabled = false; + } else if (!intel_dp->psr.active && !intel_dp->psr.busy_frontbuffer_bits) { + queue_work(dev_priv->unordered_wq, &intel_dp->psr.work); } } -- 2.34.1
