Mandate a minimum Hblank symbol cycle count between BS and BE in 8b/10b MST and 12b/132b mode. Spec: DP2.1a
v2: Affine calculation/updation of min HBlank to dp_mst (Jani) v3: moved min_hblank from struct intel_dp to intel_crtc_state (Jani) Signed-off-by: Arun R Murthy <[email protected]> --- drivers/gpu/drm/i915/display/intel_atomic.c | 1 + drivers/gpu/drm/i915/display/intel_crtc.c | 1 + .../drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_dp_mst.c | 28 +++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 4 +++ 5 files changed, 35 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c index 03dc54c802d3..24aa079efcad 100644 --- a/drivers/gpu/drm/i915/display/intel_atomic.c +++ b/drivers/gpu/drm/i915/display/intel_atomic.c @@ -278,6 +278,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc) crtc_state->dsb_color_vblank = NULL; crtc_state->dsb_commit = NULL; crtc_state->use_dsb = false; + crtc_state->min_hblank = 0; return &crtc_state->uapi; } diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c index 3c9168a57f38..472f3010bce4 100644 --- a/drivers/gpu/drm/i915/display/intel_crtc.c +++ b/drivers/gpu/drm/i915/display/intel_crtc.c @@ -184,6 +184,7 @@ void intel_crtc_state_reset(struct intel_crtc_state *crtc_state, crtc_state->scaler_state.scaler_id = -1; crtc_state->mst_master_transcoder = INVALID_TRANSCODER; crtc_state->max_link_bpp_x16 = INT_MAX; + crtc_state->min_hblank = 0; } static struct intel_crtc *intel_crtc_alloc(void) diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h index 2bb1fa64da2f..7f631fef128e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_types.h +++ b/drivers/gpu/drm/i915/display/intel_display_types.h @@ -1075,6 +1075,7 @@ struct intel_crtc_state { int max_link_bpp_x16; /* in 1/16 bpp units */ int pipe_bpp; /* in 1 bpp units */ + int min_hblank; /* min HBlank for DP2.1 */ struct intel_link_m_n dp_m_n; /* m2_n2 for eDP downclock */ diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index 1a2ff3e1cb68..2e088760a23a 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -161,6 +161,28 @@ static int intel_dp_mst_dsc_get_slice_count(const struct intel_connector *connec num_joined_pipes); } +static void intel_dp_mst_compute_min_hblank(struct intel_crtc_state *crtc_state, + struct intel_connector *intel_connector, + int bpp_x16) +{ + struct intel_encoder *intel_encoder = intel_connector->encoder; + struct intel_display *intel_display = to_intel_display(intel_encoder); + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + u32 symbol_size = intel_dp_is_uhbr(crtc_state) ? 32 : 8; + u32 hblank; + + if (DISPLAY_VER(intel_display) < 20) + return; + + /* Calculate min Hblank Link Layer Symbol Cycle Count for 8b/10b MST & 128b/132b */ + hblank = DIV_ROUND_UP((DIV_ROUND_UP(adjusted_mode->htotal - adjusted_mode->hdisplay, 4) * bpp_x16), symbol_size); + if (intel_dp_is_uhbr(crtc_state)) + crtc_state->min_hblank = (hblank > 5) ? hblank : 5; + else + crtc_state->min_hblank = (hblank > 3) ? hblank : 3; +} + static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, int max_bpp, @@ -238,6 +260,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector, true, dsc_slice_count, link_bpp_x16); + intel_dp_mst_compute_min_hblank(crtc_state, connector, link_bpp_x16); + intel_dp_mst_compute_m_n(crtc_state, connector, local_bw_overhead, link_bpp_x16, @@ -1292,6 +1316,10 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state, TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); } + if (DISPLAY_VER(dev_priv) >= 20) + intel_de_write(dev_priv, DP_MIN_HBLANK_CTL(dev_priv, trans), + pipe_config->min_hblank); + enable_bs_jitter_was(pipe_config); intel_ddi_enable_transcoder_func(encoder, pipe_config); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 405f409e9761..8aeed48f9170 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1147,6 +1147,10 @@ #define _TRANS_MULT_B 0x6102c #define TRANS_MULT(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A) +#define _DP_MIN_HBLANK_CTL_A 0x600ac +#define _DP_MIN_HBLANK_CTL_B 0x610ac +#define DP_MIN_HBLANK_CTL(dev_priv, trans) _MMIO_TRANS2(dev_priv, (trans), _DP_MIN_HBLANK_CTL_A) + /* VGA port control */ #define ADPA _MMIO(0x61100) #define PCH_ADPA _MMIO(0xe1100) -- 2.25.1
