[Intel-gfx] [PATCH 10/26] drm/i915: Make gen6_write_pdes gen6_map_page_tables

[Ben Widawsky]

Split out single mappings which will help with upcoming work. Also while
here, rename the function because it is a better description - but this
function is going away soon.

Signed-off-by: Ben Widawsky <b...@bwidawsk.net>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 39 ++++++++++++++++++++++---------------
 1 file changed, 23 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c 
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index a239196..d89054d 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -655,26 +655,33 @@ static void gen6_dump_ppgtt(struct i915_hw_ppgtt *ppgtt, 
struct seq_file *m)
        }
 }
 
-static void gen6_write_pdes(struct i915_hw_ppgtt *ppgtt)
+static void gen6_map_single(struct i915_hw_ppgtt *ppgtt,
+                           const unsigned pde_index,
+                           dma_addr_t daddr)
 {
        struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
-       gen6_gtt_pte_t __iomem *pd_addr;
        uint32_t pd_entry;
+       gen6_gtt_pte_t __iomem *pd_addr =
+               (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm + ppgtt->pd_offset / 
sizeof(gen6_gtt_pte_t);
+
+       pd_entry = GEN6_PDE_ADDR_ENCODE(daddr);
+       pd_entry |= GEN6_PDE_VALID;
+
+       writel(pd_entry, pd_addr + pde_index);
+}
+
+/* Map all the page tables found in the ppgtt structure to incrementing page
+ * directories. */
+static void gen6_map_page_tables(struct i915_hw_ppgtt *ppgtt)
+{
+       struct drm_i915_private *dev_priv = ppgtt->base.dev->dev_private;
        int i;
 
        WARN_ON(ppgtt->pd_offset & 0x3f);
-       pd_addr = (gen6_gtt_pte_t __iomem*)dev_priv->gtt.gsm +
-               ppgtt->pd_offset / sizeof(gen6_gtt_pte_t);
-       for (i = 0; i < ppgtt->num_pd_entries; i++) {
-               dma_addr_t pt_addr;
-
-               pt_addr = ppgtt->pt_dma_addr[i];
-               pd_entry = GEN6_PDE_ADDR_ENCODE(pt_addr);
-               pd_entry |= GEN6_PDE_VALID;
+       for (i = 0; i < ppgtt->num_pd_entries; i++)
+               gen6_map_single(ppgtt, i, ppgtt->pt_dma_addr[i]);
 
-               writel(pd_entry, pd_addr + i);
-       }
-       readl(pd_addr);
+       readl(dev_priv->gtt.gsm);
 }
 
 static uint32_t get_pd_offset(struct i915_hw_ppgtt *ppgtt)
@@ -1145,7 +1152,7 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
        ppgtt->pd_offset =
                ppgtt->node.start / PAGE_SIZE * sizeof(gen6_gtt_pte_t);
 
-       gen6_write_pdes(ppgtt);
+       gen6_map_page_tables(ppgtt);
 
        ppgtt->base.clear_range(&ppgtt->base, 0, ppgtt->base.total, true);
 
@@ -1319,11 +1326,11 @@ void i915_gem_restore_gtt_mappings(struct drm_device 
*dev)
                /* TODO: Perhaps it shouldn't be gen6 specific */
                if (i915_is_ggtt(vm)) {
                        if (dev_priv->mm.aliasing_ppgtt)
-                               gen6_write_pdes(dev_priv->mm.aliasing_ppgtt);
+                               
gen6_map_page_tables(dev_priv->mm.aliasing_ppgtt);
                        continue;
                }
 
-               gen6_write_pdes(container_of(vm, struct i915_hw_ppgtt, base));
+               gen6_map_page_tables(container_of(vm, struct i915_hw_ppgtt, 
base));
        }
 
        i915_gem_chipset_flush(dev);
-- 
1.9.0

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