> -----Original Message----- > From: Intel-gfx <[email protected]> On Behalf Of Jouni > Högander > Sent: 31 October 2024 13:40 > To: [email protected]; [email protected] > Cc: Hogander, Jouni <[email protected]> > Subject: [PATCH] drm/i915/psr: Disable Panel Replay as well if VRR is enabled > > Having Panel Replay enabled together with VRR is causing following errors: > > xe 0000:00:02.0: [drm] *ERROR* Timed out waiting PSR idle state xe > 0000:00:02.0: [drm] *ERROR* Fault errors on pipe A: 0x00000080 xe > 0000:00:02.0: [drm] *ERROR* CPU pipe A FIFO underrun xe 0000:00:02.0: > [drm] *ERROR* Fault errors on pipe A: 0x00040080 xe 0000:00:02.0: [drm] > *ERROR* Fault errors on pipe A: 0x00040080 > > Let's disable Panel Replay as well if VRR is enabled. > > Signed-off-by: Jouni Högander <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_psr.c | 13 ++++++------- > 1 file changed, 6 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c > b/drivers/gpu/drm/i915/display/intel_psr.c > index 0c8da1701c3a..b527c1cbb14b 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -1564,13 +1564,6 @@ static bool _psr_compute_config(struct intel_dp > *intel_dp, > const struct drm_display_mode *adjusted_mode = &crtc_state- > >hw.adjusted_mode; > int entry_setup_frames; > > - /* > - * Current PSR panels don't work reliably with VRR enabled > - * So if VRR is enabled, do not enable PSR. > - */ > - if (crtc_state->vrr.enable) > - return false; > - > if (!CAN_PSR(intel_dp)) > return false; > > @@ -1679,6 +1672,12 @@ void intel_psr_compute_config(struct intel_dp > *intel_dp, > return; > } > > + /* > + * Currently PSR/PR doesn't work reliably with VRR enabled. > + */ > + if (crtc_state->vrr.enable) > + return; > +
Reviewed-by: Mitul Golani <[email protected]> > crtc_state->has_panel_replay = > _panel_replay_compute_config(intel_dp, > crtc_state, > > conn_state); > -- > 2.34.1
