On Tue, Mar 25, 2014 at 06:01:50PM +0530, sourab.gu...@intel.com wrote: > From: Akash Goel <akash.g...@intel.com> > > This patch Removes the VS_TIMER_DISPATCH bit enable in MI MODE reg for > platforms > Gen6. > VS_TIMER_DISPATCH bit enable was earlier required as a part of > WA 'WaTimedSingleVertexDispatch', which is now applicable only to > platforms < Gen7. > > v2: Enhancing the scope of the patch to full Gen7 (Chris) > > v3: Modifying the WA condition to the cover the applicable platforms, > and adding the WA name in comments. (Ville) > > Signed-off-by: Akash Goel <akash.g...@intel.com> > Signed-off-by: Sourab Gupta <sourab.gu...@intel.com> > Tested-by: Chris Wilson <ch...@chris-wilson.co.uk> # ivb, hsw -Chris
Reviewed-by: Ville Syrjälä <ville.syrj...@linux.intel.com> > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c > b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 816137f..2ad5fe7 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -605,7 +605,8 @@ static int init_render_ring(struct intel_ring_buffer > *ring) > struct drm_i915_private *dev_priv = dev->dev_private; > int ret = init_ring_common(ring); > > - if (INTEL_INFO(dev)->gen > 3) > + /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */ > + if (INTEL_INFO(dev)->gen >= 4 && INTEL_INFO(dev)->gen < 7) > I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH)); > > /* We need to disable the AsyncFlip performance optimisations in order > -- > 1.8.5.1 -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
