Quoting Juha-Pekka Heikkila (2025-02-14 16:57:11) > Add writing of WAIT_ON_DEPTH_STALL_DONE_DISABLE for gen12, this > is performance optimization. > > Bspec: 46132 > > Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/12411 > Signed-off-by: Juha-Pekka Heikkila <[email protected]> > --- > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 3 +++ > drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++ > 2 files changed, 9 insertions(+) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > index 6dba65e54cdb..a6e50af44b46 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > @@ -409,6 +409,9 @@ > #define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8) > #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4) > > +#define GEN8_WM_CHICKEN2 MCR_REG(0x5584) > +#define WAIT_ON_DEPTH_STALL_DONE_DISABLE REG_BIT(5) > + > #define GEN9_WM_CHICKEN3 _MMIO(0x5588) > #define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c > b/drivers/gpu/drm/i915/gt/intel_workarounds.c > index db04c3ee02e2..116683ebe074 100644 > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > @@ -742,6 +742,12 @@ static void gen12_ctx_workarounds_init(struct > intel_engine_cs *engine, > /* Wa_1606376872 */ > wa_masked_en(wal, COMMON_SLICE_CHICKEN4, > DISABLE_TDC_LOAD_BALANCING_CALC); > }
Do we not have an "optional" tuning section? > + > + /* > + * This bit must be set to enable performance optimization for fast > + * clears. > + */ > + wa_mcr_write_or(wal, GEN8_WM_CHICKEN2, > WAIT_ON_DEPTH_STALL_DONE_DISABLE); This should only be applied to rcs contexts, not all. -Chris
