On Fri, Mar 21, 2025 at 02:51:14PM +0200, Jani Nikula wrote: > Usually I'd argue hardcoding values is the wrong thing to do, but in > this case, GVT looking deep into the guts of the DPLL manager for the > reference clocks is worse. This is done for BDW and BXT only, and there > shouldn't be any reason to try to be so dynamic about it. > > This helps reduce the direct pokes at display guts from non-display > code. > > Cc: Ville Syrjälä <[email protected]> > Signed-off-by: Jani Nikula <[email protected]> > --- > drivers/gpu/drm/i915/gvt/handlers.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c > b/drivers/gpu/drm/i915/gvt/handlers.c > index 4efee6797873..5e08f4df172c 100644 > --- a/drivers/gpu/drm/i915/gvt/handlers.c > +++ b/drivers/gpu/drm/i915/gvt/handlers.c > @@ -513,7 +513,7 @@ static u32 bdw_vgpu_get_dp_bitrate(struct intel_vgpu > *vgpu, enum port port) > > switch (wrpll_ctl & WRPLL_REF_MASK) { > case WRPLL_REF_PCH_SSC: > - refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.ssc; > + refclk = 135000; > break; > case WRPLL_REF_LCPLL: > refclk = 2700000; > @@ -544,7 +544,7 @@ static u32 bdw_vgpu_get_dp_bitrate(struct intel_vgpu > *vgpu, enum port port) > static u32 bxt_vgpu_get_dp_bitrate(struct intel_vgpu *vgpu, enum port port) > { > u32 dp_br = 0; > - int refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.nssc; > + int refclk = 100000; > enum dpio_phy phy = DPIO_PHY0; > enum dpio_channel ch = DPIO_CH0; > struct dpll clock = {}; > --
Reviewed-by: Zhenyu Wang <[email protected]>
