Commit f71c9b7bc35f("drm/i915/display: Prune Interlace modes for Display >=12")
defeatures interlace modes starting with display version 12. However,
there are some paths in the driver that still touch interlace-related
registers/fields for display version >= 12. So, avoid touching those
registers/fields.
Signed-off-by: Shekhar Chauhan <shekhar.chau...@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 14 ++++++++------
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 3afb85fe8536..73b1fdf0b0ff 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2686,7 +2686,7 @@ static void intel_set_transcoder_timings(const struct
intel_crtc_state *crtc_sta
crtc_vblank_start = 1;
}
- if (DISPLAY_VER(display) >= 4)
+ if (DISPLAY_VER(display) >= 4 && DISPLAY_VER(display) < 12)
intel_de_write(display,
TRANS_VSYNCSHIFT(display, cpu_transcoder),
vsyncshift);
@@ -2790,7 +2790,7 @@ static bool intel_pipe_is_interlaced(const struct
intel_crtc_state *crtc_state)
struct intel_display *display = to_intel_display(crtc_state);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
- if (DISPLAY_VER(display) == 2)
+ if (DISPLAY_VER(display) == 2 || DISPLAY_VER(display) >= 12)
return false;
if (DISPLAY_VER(display) >= 9 ||
@@ -3164,10 +3164,12 @@ static void hsw_set_transconf(const struct
intel_crtc_state *crtc_state)
if (display->platform.haswell && crtc_state->dither)
val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
- if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
- val |= TRANSCONF_INTERLACE_IF_ID_ILK;
- else
- val |= TRANSCONF_INTERLACE_PF_PD_ILK;
+ if (DISPLAY_VER(display) < 12) {
+ if (crtc_state->hw.adjusted_mode.flags &
DRM_MODE_FLAG_INTERLACE)
+ val |= TRANSCONF_INTERLACE_IF_ID_ILK;
+ else
+ val |= TRANSCONF_INTERLACE_PF_PD_ILK;
+ }
if (display->platform.haswell &&
crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
--
2.34.1
