Write DC Balance parameters to hw registers.

--v2:
- Update commit header.
- Separate crtc_state params from this patch. (Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.gol...@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 28 ++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c 
b/drivers/gpu/drm/i915/display/intel_vrr.c
index bc99701be2b5..54b91c2a0a87 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -627,6 +627,23 @@ void intel_vrr_enable(const struct intel_crtc_state 
*crtc_state)
                                       VRR_CTL_VRR_ENABLE | 
trans_vrr_ctl(crtc_state));
                }
        }
+
+       if (HAS_VRR_DC_BALANCE(display) && crtc_state->vrr.dc_balance.enable) {
+               intel_de_write(display, PIPEDMC_DCB_VMIN(display, 
cpu_transcoder),
+                              crtc_state->vrr.dc_balance.vmin - 1);
+               intel_de_write(display, PIPEDMC_DCB_VMAX(display, 
cpu_transcoder),
+                              crtc_state->vrr.dc_balance.vmax - 1);
+               intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(display, 
cpu_transcoder),
+                              crtc_state->vrr.dc_balance.max_increase);
+               intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(display, 
cpu_transcoder),
+                              crtc_state->vrr.dc_balance.max_decrease);
+               intel_de_write(display, PIPEDMC_DCB_GUARDBAND(display, 
cpu_transcoder),
+                              crtc_state->vrr.dc_balance.guardband);
+               intel_de_write(display, PIPEDMC_DCB_SLOPE(display, 
cpu_transcoder),
+                              crtc_state->vrr.dc_balance.slope);
+               intel_de_write(display, PIPEDMC_DCB_VBLANK(display, 
cpu_transcoder),
+                              crtc_state->vrr.dc_balance.vblank_target);
+       }
 }
 
 void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
@@ -637,6 +654,17 @@ void intel_vrr_disable(const struct intel_crtc_state 
*old_crtc_state)
        if (!old_crtc_state->vrr.enable)
                return;
 
+       if (HAS_VRR_DC_BALANCE(display) && 
old_crtc_state->vrr.dc_balance.enable) {
+               intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(display, 
cpu_transcoder), 0);
+               intel_de_write(display, PIPEDMC_DCB_VMIN(display, 
cpu_transcoder), 0);
+               intel_de_write(display, PIPEDMC_DCB_VMAX(display, 
cpu_transcoder), 0);
+               intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(display, 
cpu_transcoder), 0);
+               intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(display, 
cpu_transcoder), 0);
+               intel_de_write(display, PIPEDMC_DCB_GUARDBAND(display, 
cpu_transcoder), 0);
+               intel_de_write(display, PIPEDMC_DCB_SLOPE(display, 
cpu_transcoder), 0);
+               intel_de_write(display, PIPEDMC_DCB_VBLANK(display, 
cpu_transcoder), 0);
+       }
+
        if (!intel_vrr_always_use_vrr_tg(display)) {
                intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
                               trans_vrr_ctl(old_crtc_state));
-- 
2.48.1

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