Add VRR register offsets and bits to access DC Balance configuration. --v2: - Separate register definitions. (Ankit) - Remove usage of dev_priv. (Jani, Nikula)
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.gol...@intel.com> --- drivers/gpu/drm/i915/display/intel_vrr_regs.h | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h b/drivers/gpu/drm/i915/display/intel_vrr_regs.h index 6ed0e0dc97e7..8a10aec4f3cc 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h @@ -9,6 +9,54 @@ #include "intel_display_reg_defs.h" /* VRR registers */ +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A 0x604D4 +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B 0x614D4 +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_C 0x624D4 +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_D 0x634D4 +#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(display, \ + trans) _MMIO_TRANS2(display, trans, \ + _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A) + +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_A 0x604D8 +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_B 0x614D8 +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_C 0x624D8 +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_D 0x634D8 +#define TRANS_VRR_DCB_ADJ_VMAX_CFG(display, trans) _MMIO_TRANS2(display, \ + trans, \ + _TRANS_VRR_DCB_ADJ_VMAX_CFG_A) + +#define _TRANS_VRR_FLIPLINE_DCB_A 0x60418 +#define _TRANS_VRR_FLIPLINE_DCB_B 0x61418 +#define _TRANS_VRR_FLIPLINE_DCB_C 0x62418 +#define _TRANS_VRR_FLIPLINE_DCB_D 0x63418 +#define TRANS_VRR_FLIPLINE_DCB(display, trans) _MMIO_TRANS2(display, \ + trans, \ + _TRANS_VRR_FLIPLINE_DCB_A) + +#define _TRANS_VRR_VMAX_DCB_A 0x60414 +#define _TRANS_VRR_VMAX_DCB_B 0x61414 +#define _TRANS_VRR_VMAX_DCB_C 0x62414 +#define _TRANS_VRR_VMAX_DCB_D 0x63414 +#define TRANS_VRR_VMAX_DCB(display, trans) _MMIO_TRANS2(display, \ + trans, \ + _TRANS_VRR_VMAX_DCB_A) + +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_A 0x604C0 +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_B 0x614C0 +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_C 0x624C0 +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_D 0x634C0 +#define TRANS_ADAPTIVE_SYNC_DCB_CTL(display, trans) _MMIO_TRANS2(display, \ + trans, \ + _TRANS_ADAPTIVE_SYNC_DCB_CTL_A) +#define ADAPTIVE_SYNC_COUNTER_EN REG_BIT(31) +#define VRR_DCB_ADJ_FLIPLINE_CNT_MASK REG_GENMASK(31, 24) +#define VRR_DCB_ADJ_FLIPLINE_MASK REG_GENMASK(19, 0) +#define VRR_DCB_ADJ_VMAX_CNT_MASK REG_GENMASK(31, 24) +#define VRR_DCB_ADJ_VMAX_MASK REG_GENMASK(19, 0) +#define VRR_FLIPLINE_DCB_MASK REG_GENMASK(19, 0) +#define VRR_VMAX_DCB_MASK REG_GENMASK(19, 0) +#define VRR_CTL_DCB_ADJ_ENABLE REG_BIT(28) + #define _TRANS_VRR_CTL_A 0x60420 #define _TRANS_VRR_CTL_B 0x61420 #define _TRANS_VRR_CTL_C 0x62420 -- 2.48.1
