On Fri, 25 Apr 2025, Jani Nikula <[email protected]> wrote: > We'll want to relocate the unit specific functions to display, making > them inaccessible to i915 core. As there aren't that many users in i915 > core, we can just convert them to the generic VLV IOSF SB read/write > functions. > > Signed-off-by: Jani Nikula <[email protected]> > --- > drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 6 +-- > drivers/gpu/drm/i915/gt/intel_rps.c | 46 +++++++++---------- > drivers/gpu/drm/i915/soc/intel_dram.c | 4 +- > 3 files changed, 28 insertions(+), 28 deletions(-) > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c > b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c > index 0704fe763afe..288b12a02b76 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c > @@ -366,9 +366,9 @@ void intel_gt_pm_frequency_dump(struct intel_gt *gt, > struct drm_printer *p) > drm_printf(p, "SW control enabled: %s\n", > str_yes_no((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) == > GEN6_RP_MEDIA_SW_MODE)); > > - vlv_punit_get(i915); > - freq_sts = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); > - vlv_punit_put(i915); > + vlv_iosf_sb_get(i915, VLV_IOSF_SB_PUNIT);
All of the gets and puts need BIT(unit) instead of just unit as parameter. *facepalm*. Fixed in v2 [1]. BR, Jani. [1] https://lore.kernel.org/r/[email protected] > + freq_sts = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, > PUNIT_REG_GPU_FREQ_STS); > + vlv_iosf_sb_put(i915, VLV_IOSF_SB_PUNIT); > > drm_printf(p, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); > > diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c > b/drivers/gpu/drm/i915/gt/intel_rps.c > index 4f58b08ca318..e48c5bd805f1 100644 > --- a/drivers/gpu/drm/i915/gt/intel_rps.c > +++ b/drivers/gpu/drm/i915/gt/intel_rps.c > @@ -824,9 +824,9 @@ static int vlv_rps_set(struct intel_rps *rps, u8 val) > struct drm_i915_private *i915 = rps_to_i915(rps); > int err; > > - vlv_punit_get(i915); > - err = vlv_punit_write(i915, PUNIT_REG_GPU_FREQ_REQ, val); > - vlv_punit_put(i915); > + vlv_iosf_sb_get(i915, VLV_IOSF_SB_PUNIT); > + err = vlv_iosf_sb_write(i915, VLV_IOSF_SB_PUNIT, > PUNIT_REG_GPU_FREQ_REQ, val); > + vlv_iosf_sb_put(i915, VLV_IOSF_SB_PUNIT); > > GT_TRACE(rps_to_gt(rps), "set val:%x, freq:%d\n", > val, intel_gpu_freq(rps, val)); > @@ -1276,7 +1276,7 @@ static int chv_rps_max_freq(struct intel_rps *rps) > struct intel_gt *gt = rps_to_gt(rps); > u32 val; > > - val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE); > + val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, > FB_GFX_FMAX_AT_VMAX_FUSE); > > switch (gt->info.sseu.eu_total) { > case 8: > @@ -1303,7 +1303,7 @@ static int chv_rps_rpe_freq(struct intel_rps *rps) > struct drm_i915_private *i915 = rps_to_i915(rps); > u32 val; > > - val = vlv_punit_read(i915, PUNIT_GPU_DUTYCYCLE_REG); > + val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, > PUNIT_GPU_DUTYCYCLE_REG); > val >>= PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT; > > return val & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; > @@ -1314,7 +1314,7 @@ static int chv_rps_guar_freq(struct intel_rps *rps) > struct drm_i915_private *i915 = rps_to_i915(rps); > u32 val; > > - val = vlv_punit_read(i915, FB_GFX_FMAX_AT_VMAX_FUSE); > + val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, > FB_GFX_FMAX_AT_VMAX_FUSE); > > return val & FB_GFX_FREQ_FUSE_MASK; > } > @@ -1324,7 +1324,7 @@ static u32 chv_rps_min_freq(struct intel_rps *rps) > struct drm_i915_private *i915 = rps_to_i915(rps); > u32 val; > > - val = vlv_punit_read(i915, FB_GFX_FMIN_AT_VMIN_FUSE); > + val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, > FB_GFX_FMIN_AT_VMIN_FUSE); > val >>= FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT; > > return val & FB_GFX_FREQ_FUSE_MASK; > @@ -1358,14 +1358,14 @@ static bool chv_rps_enable(struct intel_rps *rps) > GEN6_PM_RP_DOWN_TIMEOUT); > > /* Setting Fixed Bias */ > - vlv_punit_get(i915); > + vlv_iosf_sb_get(i915, VLV_IOSF_SB_PUNIT); > > val = VLV_OVERRIDE_EN | VLV_SOC_TDP_EN | CHV_BIAS_CPU_50_SOC_50; > - vlv_punit_write(i915, VLV_TURBO_SOC_OVERRIDE, val); > + vlv_iosf_sb_write(i915, VLV_IOSF_SB_PUNIT, VLV_TURBO_SOC_OVERRIDE, val); > > - val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); > + val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_STS); > > - vlv_punit_put(i915); > + vlv_iosf_sb_put(i915, VLV_IOSF_SB_PUNIT); > > /* RPS code assumes GPLL is used */ > drm_WARN_ONCE(&i915->drm, (val & GPLLENABLE) == 0, > @@ -1383,7 +1383,7 @@ static int vlv_rps_guar_freq(struct intel_rps *rps) > struct drm_i915_private *i915 = rps_to_i915(rps); > u32 val, rp1; > > - val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FREQ_FUSE); > + val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_NC, IOSF_NC_FB_GFX_FREQ_FUSE); > > rp1 = val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK; > rp1 >>= FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; > @@ -1396,7 +1396,7 @@ static int vlv_rps_max_freq(struct intel_rps *rps) > struct drm_i915_private *i915 = rps_to_i915(rps); > u32 val, rp0; > > - val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FREQ_FUSE); > + val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_NC, IOSF_NC_FB_GFX_FREQ_FUSE); > > rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; > /* Clamp to max */ > @@ -1410,9 +1410,9 @@ static int vlv_rps_rpe_freq(struct intel_rps *rps) > struct drm_i915_private *i915 = rps_to_i915(rps); > u32 val, rpe; > > - val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FMAX_FUSE_LO); > + val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_NC, > IOSF_NC_FB_GFX_FMAX_FUSE_LO); > rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; > - val = vlv_nc_read(i915, IOSF_NC_FB_GFX_FMAX_FUSE_HI); > + val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_NC, > IOSF_NC_FB_GFX_FMAX_FUSE_HI); > rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; > > return rpe; > @@ -1423,7 +1423,7 @@ static int vlv_rps_min_freq(struct intel_rps *rps) > struct drm_i915_private *i915 = rps_to_i915(rps); > u32 val; > > - val = vlv_punit_read(i915, PUNIT_REG_GPU_LFM) & 0xff; > + val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_LFM) & > 0xff; > /* > * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value > * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on > @@ -1459,15 +1459,15 @@ static bool vlv_rps_enable(struct intel_rps *rps) > /* WaGsvRC0ResidencyMethod:vlv */ > rps->pm_events = GEN6_PM_RP_UP_EI_EXPIRED; > > - vlv_punit_get(i915); > + vlv_iosf_sb_get(i915, VLV_IOSF_SB_PUNIT); > > /* Setting Fixed Bias */ > val = VLV_OVERRIDE_EN | VLV_SOC_TDP_EN | VLV_BIAS_CPU_125_SOC_875; > - vlv_punit_write(i915, VLV_TURBO_SOC_OVERRIDE, val); > + vlv_iosf_sb_write(i915, VLV_IOSF_SB_PUNIT, VLV_TURBO_SOC_OVERRIDE, val); > > - val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); > + val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_STS); > > - vlv_punit_put(i915); > + vlv_iosf_sb_put(i915, VLV_IOSF_SB_PUNIT); > > /* RPS code assumes GPLL is used */ > drm_WARN_ONCE(&i915->drm, (val & GPLLENABLE) == 0, > @@ -2115,9 +2115,9 @@ static u32 __read_cagf(struct intel_rps *rps, bool > take_fw) > } else if (GRAPHICS_VER(i915) >= 12) { > r = GEN12_RPSTAT1; > } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) { > - vlv_punit_get(i915); > - freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); > - vlv_punit_put(i915); > + vlv_iosf_sb_get(i915, VLV_IOSF_SB_PUNIT); > + freq = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, > PUNIT_REG_GPU_FREQ_STS); > + vlv_iosf_sb_put(i915, VLV_IOSF_SB_PUNIT); > } else if (GRAPHICS_VER(i915) >= 6) { > r = GEN6_RPSTAT1; > } else { > diff --git a/drivers/gpu/drm/i915/soc/intel_dram.c > b/drivers/gpu/drm/i915/soc/intel_dram.c > index 0b92ab4e9fb9..e8d6bd116b44 100644 > --- a/drivers/gpu/drm/i915/soc/intel_dram.c > +++ b/drivers/gpu/drm/i915/soc/intel_dram.c > @@ -98,7 +98,7 @@ static unsigned int chv_mem_freq(struct drm_i915_private > *i915) > u32 val; > > vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCK)); > - val = vlv_cck_read(i915, CCK_FUSE_REG); > + val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_CCK, CCK_FUSE_REG); > vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCK)); > > switch ((val >> 2) & 0x7) { > @@ -114,7 +114,7 @@ static unsigned int vlv_mem_freq(struct drm_i915_private > *i915) > u32 val; > > vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT)); > - val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS); > + val = vlv_iosf_sb_read(i915, VLV_IOSF_SB_PUNIT, PUNIT_REG_GPU_FREQ_STS); > vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT)); > > switch ((val >> 6) & 3) { -- Jani Nikula, Intel
