On Fri, Apr 04, 2014 at 05:14:38PM +0530, sourab.gu...@intel.com wrote: > From: Akash Goel <akash.g...@intel.com> > > On Gen4+ platforms (except BDW), Render Cache Operational flush > cannot be enabled. > This WA is apparently required for all Gen4+ platforms,except BDW. > In BDW, the bit has been repurposed otherwise. > This has been tested only on vlv. > > v2: Corrected the code regarding the wrong usage of > MASKED_BIT_DISABLE (Chris) > > v3: Enhancing the scope of WA to Gen4+ platforms except BDW (Ville) > > v4: Adding WA for g4x, crestline, broadwater (Ville) > > Signed-off-by: Akash Goel <akash.g...@intel.com> > Signed-off-by: Sourab Gupta <sourab.gu...@intel.com> > Reviewed-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
Note that we now have a redundant CM0_RC_OP_FLUSH_DISABLE (which fails the name test anyway). I'm also not a fan of enable(RC_OP_FLUSH_ENABLE)/disable(RC_OP_FLUSH_ENABLE) either, but as far as the content goes, Reviewed-by: Chris Wilson <ch...@chris-wilson.co.uk> Sadly, it didn't appear to fix any bugs. -Chris -- Chris Wilson, Intel Open Source Technology Centre _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
