Write DC Balance parameters to hw registers.
--v2:
- Update commit header.
- Separate crtc_state params from this patch. (Ankit)
--v3:
- Write registers at compute config.
- Update condition for write.
--v4:
- Address issue with state checker.
--v5:
- Initialise some more dc balance register while enabling VRR.
--v6:
- FLIPLINE_CFG need to be configure at last, as it is double buffer
arming point.
Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.gol...@intel.com>
Reviewed-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
---
drivers/gpu/drm/i915/display/intel_vrr.c | 43 ++++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 07cd7cb38b97..ce23bcab1033 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -622,6 +622,8 @@ void intel_vrr_enable(const struct intel_crtc_state
*crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ enum pipe pipe = crtc->pipe;
if (!crtc_state->vrr.enable)
return;
@@ -648,16 +650,57 @@ void intel_vrr_enable(const struct intel_crtc_state
*crtc_state)
VRR_CTL_VRR_ENABLE |
trans_vrr_ctl(crtc_state));
}
}
+
+ if (crtc_state->vrr.dc_balance.enable) {
+ intel_de_write(display,
TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder),
+ VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1));
+ intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder),
+ VRR_DCB_VMAX(crtc_state->vrr.vmax - 1));
+ intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder),
+ VRR_DCB_FLIPLINE(crtc_state->vrr.flipline - 1));
+ intel_de_write(display,
TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder),
+ VRR_DCB_ADJ_FLIPLINE(crtc_state->vrr.flipline -
1));
+ intel_de_write(display, PIPEDMC_DCB_VMIN(pipe),
+ crtc_state->vrr.dc_balance.vmin - 1);
+ intel_de_write(display, PIPEDMC_DCB_VMAX(pipe),
+ crtc_state->vrr.dc_balance.vmax - 1);
+ intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe),
+ crtc_state->vrr.dc_balance.max_increase);
+ intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe),
+ crtc_state->vrr.dc_balance.max_decrease);
+ intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe),
+ crtc_state->vrr.dc_balance.guardband);
+ intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe),
+ crtc_state->vrr.dc_balance.slope);
+ intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe),
+ crtc_state->vrr.dc_balance.vblank_target);
+ }
}
void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
{
struct intel_display *display = to_intel_display(old_crtc_state);
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ enum pipe pipe = crtc->pipe;
if (!old_crtc_state->vrr.enable)
return;
+ if (old_crtc_state->vrr.dc_balance.enable) {
+ intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);
+ intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);
+ intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe), 0);
+ intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe), 0);
+ intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe), 0);
+ intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe), 0);
+ intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe), 0);
+ intel_de_write(display,
TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder), 0);
+ intel_de_write(display,
TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), 0);
+ intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), 0);
+ intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder),
0);
+ }
+
if (!intel_vrr_always_use_vrr_tg(display)) {
intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
trans_vrr_ctl(old_crtc_state));
--
2.48.1
