On Tue, 24 Jun 2025, Mitul Golani <mitulkumar.ajitkumar.gol...@intel.com> wrote:
> Add VRR register offsets and bits to access DC Balance configuration.
>
> --v2:
> - Separate register definitions. (Ankit)
> - Remove usage of dev_priv. (Jani, Nikula)
>
> --v3:
> - Convert register address offset, from capital to small. (Ankit)
> - Move mask bits near to register offsets. (Ankit)
>
> --v4:
> - Use _MMIO_TRANS wherever possible. (Jani)
>
> Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.gol...@intel.com>
> Reviewed-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
I just took the time to clean this file up. See commit 880e07d53849
("drm/i915/vrr: fix register file style"). Please follow the style.
> ---
> drivers/gpu/drm/i915/display/intel_vrr_regs.h | 45 +++++++++++++++++++
> 1 file changed, 45 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> index ba9b9215dc11..c5cba5879f40 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vrr_regs.h
> @@ -8,6 +8,50 @@
>
> #include "intel_display_reg_defs.h"
>
> +/* VRR registers */
> +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A 0x604d4
> +#define _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B 0x614d4
> +#define TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(trans) _MMIO_TRANS(trans, \
> +
> _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_A, \
> +
> _TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_B)
> +#define VRR_DCB_ADJ_FLIPLINE_CNT_MASK REG_GENMASK(31, 24)
> +#define VRR_DCB_ADJ_FLIPLINE_MASK REG_GENMASK(19, 0)
> +#define VRR_DCB_ADJ_FLIPLINE(flipline)
> REG_FIELD_PREP(VRR_DCB_ADJ_FLIPLINE_MASK, \
> + (flipline))
> +
> +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_A 0x604d8
> +#define _TRANS_VRR_DCB_ADJ_VMAX_CFG_B 0x614d8
> +#define TRANS_VRR_DCB_ADJ_VMAX_CFG(trans) _MMIO_TRANS(trans, \
> +
> _TRANS_VRR_DCB_ADJ_VMAX_CFG_A, \
> +
> _TRANS_VRR_DCB_ADJ_VMAX_CFG_B)
> +#define VRR_DCB_ADJ_VMAX_CNT_MASK REG_GENMASK(31, 24)
> +#define VRR_DCB_ADJ_VMAX_MASK REG_GENMASK(19, 0)
> +#define VRR_DCB_ADJ_VMAX(vmax)
> REG_FIELD_PREP(VRR_DCB_ADJ_VMAX_MASK, (vmax))
> +
> +#define _TRANS_VRR_DCB_FLIPLINE_A 0x60418
> +#define _TRANS_VRR_DCB_FLIPLINE_B 0x61418
> +#define TRANS_VRR_DCB_FLIPLINE(trans) _MMIO_TRANS(trans, \
> +
> _TRANS_VRR_DCB_FLIPLINE_A, \
> +
> _TRANS_VRR_DCB_FLIPLINE_B)
> +#define VRR_DCB_FLIPLINE_MASK REG_GENMASK(19, 0)
> +#define VRR_DCB_FLIPLINE(flipline)
> REG_FIELD_PREP(VRR_DCB_FLIPLINE_MASK, \
> + (flipline))
> +
> +#define _TRANS_VRR_DCB_VMAX_A 0x60414
> +#define _TRANS_VRR_DCB_VMAX_B 0x61414
> +#define TRANS_VRR_DCB_VMAX(trans) _MMIO_TRANS(trans, \
> +
> _TRANS_VRR_DCB_VMAX_A, \
> +
> _TRANS_VRR_DCB_VMAX_B)
> +#define VRR_DCB_VMAX_MASK REG_GENMASK(19, 0)
> +#define VRR_DCB_VMAX(vmax)
> REG_FIELD_PREP(VRR_DCB_VMAX_MASK, (vmax))
> +
> +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_A 0x604c0
> +#define _TRANS_ADAPTIVE_SYNC_DCB_CTL_B 0x614c0
> +#define TRANS_ADAPTIVE_SYNC_DCB_CTL(trans) _MMIO_TRANS(trans, \
> +
> _TRANS_ADAPTIVE_SYNC_DCB_CTL_A, \
> +
> _TRANS_ADAPTIVE_SYNC_DCB_CTL_B)
> +#define ADAPTIVE_SYNC_COUNTER_EN REG_BIT(31)
> +
> #define _TRANS_VRR_CTL_A 0x60420
> #define _TRANS_VRR_CTL_B 0x61420
> #define _TRANS_VRR_CTL_C 0x62420
> @@ -20,6 +64,7 @@
> #define VRR_CTL_PIPELINE_FULL_MASK REG_GENMASK(10, 3)
> #define VRR_CTL_PIPELINE_FULL(x)
> REG_FIELD_PREP(VRR_CTL_PIPELINE_FULL_MASK, (x))
> #define VRR_CTL_PIPELINE_FULL_OVERRIDE REG_BIT(0)
> +#define VRR_CTL_DCB_ADJ_ENABLE REG_BIT(28)
Highest to lowest bit.
> #define XELPD_VRR_CTL_VRR_GUARDBAND_MASK REG_GENMASK(15, 0)
> #define XELPD_VRR_CTL_VRR_GUARDBAND(x)
> REG_FIELD_PREP(XELPD_VRR_CTL_VRR_GUARDBAND_MASK, (x))
--
Jani Nikula, Intel
