Introduce a helper to compute the max link wake latency when using
Auxless/Aux wake mechanism for PSR/Panel Replay/LOBF features.
This will be used to compute the minimum guardband so that the link wake
latencies are accounted and these features work smoothly for higher
refresh rate panels.
Bspec: 70151, 71477
Signed-off-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>
---
drivers/gpu/drm/i915/display/intel_psr.c | 64 ++++++++++++++++++++++++
drivers/gpu/drm/i915/display/intel_psr.h | 3 ++
2 files changed, 67 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
b/drivers/gpu/drm/i915/display/intel_psr.c
index 6bd3454bb00e..6cdaff3ccc9f 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -33,6 +33,7 @@
#include "intel_atomic.h"
#include "intel_crtc.h"
#include "intel_cursor_regs.h"
+#include "intel_cx0_phy.h"
#include "intel_ddi.h"
#include "intel_de.h"
#include "intel_display_irq.h"
@@ -4249,3 +4250,66 @@ bool intel_psr_needs_alpm_aux_less(struct intel_dp
*intel_dp,
{
return intel_dp_is_edp(intel_dp) && crtc_state->has_panel_replay;
}
+
+static
+int intel_psr_compute_aux_wake_latency(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state)
+{
+#define TFW_EXIT_LATENCY_MS 20000
+#define FAST_WAKE_LATENCY_MS 12000 /* Preamble: 8us; PHY wake: 4us */
+ struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ int aux_wake_latency_us;
+ int io_buffer_wake_ms;
+
+ io_buffer_wake_ms = intel_encoder_is_c10phy(encoder) ? 9790 : 14790;
+
+ aux_wake_latency_us =
+ DIV_ROUND_UP(io_buffer_wake_ms + TFW_EXIT_LATENCY_MS +
FAST_WAKE_LATENCY_MS, 1000);
+
+ return aux_wake_latency_us;
+}
+
+static
+int intel_psr_compute_auxless_latency(struct intel_crtc_state *crtc_state)
+{
+#define PHY_ESTABLISHMENT_PERIOD_MS 50000
+#define LFPS_PERIOD_MS 800
+#define SILENCE_MAX_MS 180
+ int linkrate_mhz = crtc_state->port_clock / 1000;
+ int clock_data_switch_ms;
+ int auxless_latency_us;
+ int time_ml_phy_lock_ms;
+ int num_ml_phy_lock;
+ /*
+ * TPS4 length = 252
+ * tML_PHY_LOCK = TPS4 Length * ( 10 / (Link Rate in MHz) )
+ * Number ML_PHY_LOCK = ( 7 + CEILING(6.5us / tML_PHY_LOCK ) + 1)
+ * t2 = Number ML_PHY_LOCK * tML_PHY_LOCK
+ * tCDS term = 2 * t2
+ * =>tCDS_term = 2 * (7 * (252 * (10 /linkrate))+6.5)
+ */
+ time_ml_phy_lock_ms = (1000 * 252 * 10) / linkrate_mhz;
+ num_ml_phy_lock = 7 + DIV_ROUND_UP(6500 * 1000, time_ml_phy_lock_ms) /
1000 + 1;
+ clock_data_switch_ms = 2 * time_ml_phy_lock_ms * num_ml_phy_lock;
+
+ auxless_latency_us = (LFPS_PERIOD_MS + SILENCE_MAX_MS +
PHY_ESTABLISHMENT_PERIOD_MS +
+ clock_data_switch_ms) / 1000;
+
+ return auxless_latency_us;
+}
+
+int intel_psr_compute_max_link_wake_latency(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state,
+ bool assume_all_enabled)
+{
+ int aux_wake_latency = 0;
+ int auxless_latency = 0;
+
+ if (assume_all_enabled || crtc_state->has_sel_update)
+ auxless_latency = intel_psr_compute_aux_wake_latency(intel_dp,
crtc_state);
+
+ if (assume_all_enabled || crtc_state->has_panel_replay)
+ aux_wake_latency =
intel_psr_compute_auxless_latency(crtc_state);
+
+ return max(auxless_latency, aux_wake_latency);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
b/drivers/gpu/drm/i915/display/intel_psr.h
index 9b061a22361f..c58d29620b49 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -81,5 +81,8 @@ void intel_psr_debugfs_register(struct intel_display
*display);
bool intel_psr_needs_alpm(struct intel_dp *intel_dp, const struct
intel_crtc_state *crtc_state);
bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp,
const struct intel_crtc_state *crtc_state);
+int intel_psr_compute_max_link_wake_latency(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state,
+ bool assume_all_enabled);
#endif /* __INTEL_PSR_H__ */
--
2.45.2
