On Thu, 18 Sep 2025, Ville Syrjälä <[email protected]> wrote:
> On Thu, Sep 18, 2025 at 04:38:35PM +0300, Jani Nikula wrote:
>> Abstract ilk_display_irq_reset(), moving display related reset
>> there. This results in a slightly different order between GT and PCH
>> reset, hopefully with no impact.
>>
>> v3: Reset display first (Ville)
>>
>> v2: Also move GEN7_ERR_INT (Ville)
>>
>> Signed-off-by: Jani Nikula <[email protected]>
>
> Reviewed-by: Ville Syrjälä <[email protected]>
Thanks a lot, series pushed to din.
BR,
Jani.
>
>> ---
>> .../gpu/drm/i915/display/intel_display_irq.c | 20 ++++++++++++++++++-
>> .../gpu/drm/i915/display/intel_display_irq.h | 2 +-
>> drivers/gpu/drm/i915/i915_irq.c | 16 ++-------------
>> 3 files changed, 22 insertions(+), 16 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
>> b/drivers/gpu/drm/i915/display/intel_display_irq.c
>> index 93c2e42f98c9..c6f367e6159e 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
>> @@ -1985,7 +1985,7 @@ void vlv_display_irq_postinstall(struct intel_display
>> *display)
>> spin_unlock_irq(&display->irq.lock);
>> }
>>
>> -void ibx_display_irq_reset(struct intel_display *display)
>> +static void ibx_display_irq_reset(struct intel_display *display)
>> {
>> if (HAS_PCH_NOP(display))
>> return;
>> @@ -1996,6 +1996,24 @@ void ibx_display_irq_reset(struct intel_display
>> *display)
>> intel_de_write(display, SERR_INT, 0xffffffff);
>> }
>>
>> +void ilk_display_irq_reset(struct intel_display *display)
>> +{
>> + struct intel_uncore *uncore = to_intel_uncore(display->drm);
>> +
>> + gen2_irq_reset(uncore, DE_IRQ_REGS);
>> + display->irq.ilk_de_imr_mask = ~0u;
>> +
>> + if (DISPLAY_VER(display) == 7)
>> + intel_de_write(display, GEN7_ERR_INT, 0xffffffff);
>> +
>> + if (display->platform.haswell) {
>> + intel_de_write(display, EDP_PSR_IMR, 0xffffffff);
>> + intel_de_write(display, EDP_PSR_IIR, 0xffffffff);
>> + }
>> +
>> + ibx_display_irq_reset(display);
>> +}
>> +
>> void gen8_display_irq_reset(struct intel_display *display)
>> {
>> enum pipe pipe;
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.h
>> b/drivers/gpu/drm/i915/display/intel_display_irq.h
>> index c66db3851da4..cee120347064 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_irq.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.h
>> @@ -56,7 +56,7 @@ u32 gen11_gu_misc_irq_ack(struct intel_display *display,
>> const u32 master_ctl);
>> void gen11_gu_misc_irq_handler(struct intel_display *display, const u32
>> iir);
>>
>> void i9xx_display_irq_reset(struct intel_display *display);
>> -void ibx_display_irq_reset(struct intel_display *display);
>> +void ilk_display_irq_reset(struct intel_display *display);
>> void vlv_display_irq_reset(struct intel_display *display);
>> void gen8_display_irq_reset(struct intel_display *display);
>> void gen11_display_irq_reset(struct intel_display *display);
>> diff --git a/drivers/gpu/drm/i915/i915_irq.c
>> b/drivers/gpu/drm/i915/i915_irq.c
>> index ab65402bc6bf..7c7c6dcbce88 100644
>> --- a/drivers/gpu/drm/i915/i915_irq.c
>> +++ b/drivers/gpu/drm/i915/i915_irq.c
>> @@ -656,22 +656,10 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
>> static void ilk_irq_reset(struct drm_i915_private *dev_priv)
>> {
>> struct intel_display *display = dev_priv->display;
>> - struct intel_uncore *uncore = &dev_priv->uncore;
>> -
>> - gen2_irq_reset(uncore, DE_IRQ_REGS);
>> - display->irq.ilk_de_imr_mask = ~0u;
>> -
>> - if (GRAPHICS_VER(dev_priv) == 7)
>> - intel_uncore_write(uncore, GEN7_ERR_INT, 0xffffffff);
>> -
>> - if (IS_HASWELL(dev_priv)) {
>> - intel_uncore_write(uncore, EDP_PSR_IMR, 0xffffffff);
>> - intel_uncore_write(uncore, EDP_PSR_IIR, 0xffffffff);
>> - }
>>
>> + /* The master interrupt enable is in DEIER, reset display irq first */
>> + ilk_display_irq_reset(display);
>> gen5_gt_irq_reset(to_gt(dev_priv));
>> -
>> - ibx_display_irq_reset(display);
>> }
>>
>> static void valleyview_irq_reset(struct drm_i915_private *dev_priv)
>> --
>> 2.47.3
--
Jani Nikula, Intel
