This series introduces support for the DPLL framework on MTL+ platforms.
It begins with a set of cleanups and helper refactors, then gradually
adds the necessary infrastructure for dpll framework, followed by
extensions to support additional platforms. The final patch enables the
DPLL framework for MTL+.
The patches are organized as follows:
* Fixes and refactoring
* Tracking additional PLL/PHY HW state in the PLL SW state
* Align the Cx0 PHY PLL state compute/readout and enabling functions on MTL+
as expected by the PLL manager
* Add the Cx0 PHY PLL manager/PLL hooks for MTL+
* Enable the PLL manager for MTL+ platforms
Note:
This series does not include the following features that would
require attention as a follow up series
* Add support for:
- CMTG
- C20 PHY PLL on port B
* Decouple PLL code from encoders for better isolation of PLL code internals
Imre Deak (22):
drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/DP_RATE
field macros
drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/IS_DP flag
macro
drm/i915/display: Sanitize
PHY_C20_VDR_CUSTOM_SERDES_RATE/CONTEXT_TOGGLE flag macro
drm/i915/display: Sanitize PHY_C20_VDR_CUSTOM_SERDES_RATE/IS_HDMI_FRL
flag macro
drm/i915/display: Fix PHY_C20_VDR_CUSTOM_SERDES_RATE programming
drm/i915/display: Fix PHY_C20_VDR_HDMI_RATE programming
drm/i915/display: Add missing clock to C10 PHY state compute/HW
readout
drm/i915/display: Factor out C10 msgbus access start/end helpers
drm/i915/display: Sanitize setting the Cx0 PLL use_c10 flag
drm/i915/display: Sanitize calculating C20 PLL state from tables
drm/i915/display: Track the C20 PHY VDR state in the PLL state
drm/i915/display: Move definition of Cx0 PHY functions earlier
drm/i915/display: Add macro to get DDI port width from a register
value
drm/i915/display: Track the Cx0 PHY enabled lane count in the PLL
state
drm/i915/display: Sanitize C10 PHY PLL SSC register setup
drm/i915/display: Read out the Cx0 PHY SSC enabled state
drm/i915/display: Determine Cx0 PLL DP mode from PLL state
drm/i915/display: Determine Cx0 PLL port clock from PLL state
drm/i915/display: Zero Cx0 PLL state before compute and HW readout
drm/i915/display: Print additional Cx0 PLL HW state
drm/i915/display: PLL verify debug state print
drm/i915/display: Add Thunderbolt support
Mika Kahola (17):
drm/i915/display: Rename TBT functions to be ICL specific
drm/i915/display: Remove state verification
drm/i915/display: PLL information for MTL+
drm/i915/display: Update C10/C20 state calculation
drm/i915/display: Compute plls for MTL+ platform
drm/i915/display: MTL+ .get_dplls
drm/i915/display: MTL+ .put_dplls
drm/i915/display: Add .update_active_dpll
drm/i915/display: Add .update_dpll_ref_clks
drm/i915/display: Add .dump_hw_state
drm/i915/display: Add .compare_hw_state
drm/i915/display: Add .get_hw_state to MTL+ platforms
drm/i915/display: Add .get_freq to MTL+ platforms
drm/i915/display: Add .crtc_get_dpll hook
drm/i915/display: Add .enable_clock on DDI for MTL+ platforms
drm/i915/display: Get configuration for C10 and C20
drm/i915/display: Enable dpll framework for MTL+
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 897 ++++++++++--------
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 25 +-
.../gpu/drm/i915/display/intel_cx0_phy_regs.h | 10 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 76 +-
drivers/gpu/drm/i915/display/intel_display.c | 32 -
.../gpu/drm/i915/display/intel_display_regs.h | 7 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 24 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 297 +++++-
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 7 +
.../drm/i915/display/intel_modeset_verify.c | 1 -
.../drm/i915/display/intel_snps_hdmi_pll.c | 2 +
11 files changed, 884 insertions(+), 494 deletions(-)
--
2.34.1
