On Wed, Oct 15, 2025 at 12:15:16AM -0300, Gustavo Sousa wrote: > Add CDCLK table for Xe3p_LPD. > > Just as with Xe3_LPD, we don't need to send voltage index info in the > PMDemand message, so we are able to re-use xe3lpd_cdclk_funcs. > > With the new CDCLK table, we also need to update the maximum CDCLK value > returned by intel_update_max_cdclk(). > > Bspec: 68861, 68863 > Signed-off-by: Gustavo Sousa <[email protected]>
Table matches the spec and I don't see any new programming/register changes introduced by this IP. Reviewed-by: Matt Roper <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_cdclk.c | 44 > ++++++++++++++++++++++++++++-- > 1 file changed, 42 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c > b/drivers/gpu/drm/i915/display/intel_cdclk.c > index f2e092f89ddd..ffd8cab2d565 100644 > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c > @@ -1534,6 +1534,41 @@ static const struct intel_cdclk_vals > xe3lpd_cdclk_table[] = { > {} > }; > > +static const struct intel_cdclk_vals xe3p_lpd_cdclk_table[] = { > + { .refclk = 38400, .cdclk = 151200, .ratio = 21, .waveform = 0xa4a4 }, > + { .refclk = 38400, .cdclk = 176400, .ratio = 21, .waveform = 0xaa54 }, > + { .refclk = 38400, .cdclk = 201600, .ratio = 21, .waveform = 0xaaaa }, > + { .refclk = 38400, .cdclk = 226800, .ratio = 21, .waveform = 0xad5a }, > + { .refclk = 38400, .cdclk = 252000, .ratio = 21, .waveform = 0xb6b6 }, > + { .refclk = 38400, .cdclk = 277200, .ratio = 21, .waveform = 0xdbb6 }, > + { .refclk = 38400, .cdclk = 302400, .ratio = 21, .waveform = 0xeeee }, > + { .refclk = 38400, .cdclk = 327600, .ratio = 21, .waveform = 0xf7de }, > + { .refclk = 38400, .cdclk = 352800, .ratio = 21, .waveform = 0xfefe }, > + { .refclk = 38400, .cdclk = 378000, .ratio = 21, .waveform = 0xfffe }, > + { .refclk = 38400, .cdclk = 403200, .ratio = 21, .waveform = 0xffff }, > + { .refclk = 38400, .cdclk = 422400, .ratio = 22, .waveform = 0xffff }, > + { .refclk = 38400, .cdclk = 441600, .ratio = 23, .waveform = 0xffff }, > + { .refclk = 38400, .cdclk = 460800, .ratio = 24, .waveform = 0xffff }, > + { .refclk = 38400, .cdclk = 480000, .ratio = 25, .waveform = 0xffff }, > + { .refclk = 38400, .cdclk = 499200, .ratio = 26, .waveform = 0xffff }, > + { .refclk = 38400, .cdclk = 518400, .ratio = 27, .waveform = 0xffff }, > + { .refclk = 38400, .cdclk = 537600, .ratio = 28, .waveform = 0xffff }, > + { .refclk = 38400, .cdclk = 556800, .ratio = 29, .waveform = 0xffff }, > + { .refclk = 38400, .cdclk = 576000, .ratio = 30, .waveform = 0xffff }, > + { .refclk = 38400, .cdclk = 595200, .ratio = 31, .waveform = 0xffff }, > + { .refclk = 38400, .cdclk = 614400, .ratio = 32, .waveform = 0xffff }, > + { .refclk = 38400, .cdclk = 633600, .ratio = 33, .waveform = 0xffff }, > + { .refclk = 38400, .cdclk = 652800, .ratio = 34, .waveform = 0xffff }, > + { .refclk = 38400, .cdclk = 672000, .ratio = 35, .waveform = 0xffff }, > + { .refclk = 38400, .cdclk = 691200, .ratio = 36, .waveform = 0xffff }, > + { .refclk = 38400, .cdclk = 710400, .ratio = 37, .waveform = 0xffff }, > + { .refclk = 38400, .cdclk = 729600, .ratio = 38, .waveform = 0xffff }, > + { .refclk = 38400, .cdclk = 748800, .ratio = 39, .waveform = 0xffff }, > + { .refclk = 38400, .cdclk = 768000, .ratio = 40, .waveform = 0xffff }, > + { .refclk = 38400, .cdclk = 787200, .ratio = 41, .waveform = 0xffff }, > + {} > +}; > + > static const int cdclk_squash_len = 16; > > static int cdclk_squash_divider(u16 waveform) > @@ -3555,7 +3590,9 @@ static int intel_compute_max_dotclk(struct > intel_display *display) > */ > void intel_update_max_cdclk(struct intel_display *display) > { > - if (DISPLAY_VERx100(display) >= 3002) { > + if (DISPLAY_VER(display) >= 35) { > + display->cdclk.max_cdclk_freq = 787200; > + } else if (DISPLAY_VERx100(display) >= 3002) { > display->cdclk.max_cdclk_freq = 480000; > } else if (DISPLAY_VER(display) >= 30) { > display->cdclk.max_cdclk_freq = 691200; > @@ -3906,7 +3943,10 @@ static const struct intel_cdclk_funcs i830_cdclk_funcs > = { > */ > void intel_init_cdclk_hooks(struct intel_display *display) > { > - if (DISPLAY_VER(display) >= 30) { > + if (DISPLAY_VER(display) >= 35) { > + display->funcs.cdclk = &xe3lpd_cdclk_funcs; > + display->cdclk.table = xe3p_lpd_cdclk_table; > + } else if (DISPLAY_VER(display) >= 30) { > display->funcs.cdclk = &xe3lpd_cdclk_funcs; > display->cdclk.table = xe3lpd_cdclk_table; > } else if (DISPLAY_VER(display) >= 20) { > > -- > 2.51.0 > -- Matt Roper Graphics Software Engineer Linux GPU Platform Enablement Intel Corporation
