On Fri, Oct 10, 2025 at 02:07:51PM +0300, Jani Nikula wrote: > Gen 2 platforms actually have 128-byte Y-tile, it's just different from > the 128-byte Y-tile on i945+. Make the HAS_128_BYTE_Y_TILING() feature > check macro and its usage slightly less convoluted by including gen 2 in > it. > > i915_tiling_ok() would strictly not need changing, but separate the if > clauses to emphasize gen 2 X-tile also being 128 bytes. > > Suggested-by: Ville Syrjälä <[email protected]> > Signed-off-by: Jani Nikula <[email protected]>
I think I want to redo the gem side tile size stuff with a bigger hammer a bit at some point, but this seems fine for now. Reviewed-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_fb.c | 2 +- > drivers/gpu/drm/i915/gem/i915_gem_tiling.c | 5 +++-- > drivers/gpu/drm/i915/i915_drv.h | 3 +-- > 3 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_fb.c > b/drivers/gpu/drm/i915/display/intel_fb.c > index 99823ef42ef1..3bfd211d64ba 100644 > --- a/drivers/gpu/drm/i915/display/intel_fb.c > +++ b/drivers/gpu/drm/i915/display/intel_fb.c > @@ -814,7 +814,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, > int color_plane) > return 64; > fallthrough; > case I915_FORMAT_MOD_Y_TILED: > - if (DISPLAY_VER(display) == 2 || HAS_128_BYTE_Y_TILING(i915)) > + if (HAS_128_BYTE_Y_TILING(i915)) > return 128; > else > return 512; > diff --git a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c > b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c > index 5a296ba3758a..567b97d28d30 100644 > --- a/drivers/gpu/drm/i915/gem/i915_gem_tiling.c > +++ b/drivers/gpu/drm/i915/gem/i915_gem_tiling.c > @@ -145,8 +145,9 @@ i915_tiling_ok(struct drm_i915_gem_object *obj, > return false; > } > > - if (GRAPHICS_VER(i915) == 2 || > - (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915))) > + if (tiling == I915_TILING_Y && HAS_128_BYTE_Y_TILING(i915)) > + tile_width = 128; > + else if (GRAPHICS_VER(i915) == 2) > tile_width = 128; > else > tile_width = 512; > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 6e159bb8ad2f..4b66e5d017d9 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -602,8 +602,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915, > /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte > * rows, which changed the alignment requirements and fence programming. > */ > -#define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \ > - !(IS_I915G(i915) || IS_I915GM(i915))) > +#define HAS_128_BYTE_Y_TILING(i915) (!IS_I915G(i915) && !IS_I915GM(i915)) > > #define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6) > #define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p) > -- > 2.47.3 -- Ville Syrjälä Intel
