On Wed, Oct 15, 2025 at 12:52:16PM +0530, Ankit Nautiyal wrote:
> As we move towards using a shorter, optimized guardband, we need to adjust
> how the delayed vblank start is computed.
> 
> Adjust the crtc_vblank_start using Vmin Vtotal - guardband only when
> intel_vrr_always_use_vrr_tg() is true. Also update the
> pipe_mode->crtc_vblank_start which is derived from
> adjusted_mode->crtc_vblank_start in intel_crtc_compute_pipe_mode().
> 
> To maintain consistency between the computed and readout paths, also update
> the readout logic in intel_vrr_get_config() to overwrite crtc_vblank_start
> with the same value (vtotal - guardband) on platforms with always-on
> VRR TG. pipe_mode is derived
> 
> This also paves way for guardband optimization, by handling the movement of
> the crtc_vblank_start for platforms that have VRR TG always active.
> 
> v2: Drop the helper and add the adjustment directly to
>     intel_vrr_compute_guardband(). (Ville)
> v3: Use adjusted_mode.crtc_vtotal instead of vmin and include the readout
>     logic to keep the compute and readout paths in sync. (Ville)
> v4: Also set pipe_mode->crtc_vblank_start as its derived from
>     adjusted_mode. (Ville)
> 
> Signed-off-by: Ankit Nautiyal <[email protected]>
> ---
>  drivers/gpu/drm/i915/display/intel_vrr.c | 23 ++++++++++++++++++++++-
>  1 file changed, 22 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c 
> b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 8d71d7dc9d12..1cfcc31bd899 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -436,7 +436,8 @@ intel_vrr_max_guardband(struct intel_crtc_state 
> *crtc_state)
>  void intel_vrr_compute_guardband(struct intel_crtc_state *crtc_state)
>  {
>       struct intel_display *display = to_intel_display(crtc_state);
> -     const struct drm_display_mode *adjusted_mode = 
> &crtc_state->hw.adjusted_mode;
> +     struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> +     struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
>  
>       if (!intel_vrr_possible(crtc_state))
>               return;
> @@ -444,6 +445,13 @@ void intel_vrr_compute_guardband(struct intel_crtc_state 
> *crtc_state)
>       crtc_state->vrr.guardband = min(crtc_state->vrr.vmin - 
> adjusted_mode->crtc_vdisplay,
>                                       intel_vrr_max_guardband(crtc_state));
>  
> +     if (intel_vrr_always_use_vrr_tg(display)) {
> +             adjusted_mode->crtc_vblank_start  =
> +                     adjusted_mode->crtc_vtotal - crtc_state->vrr.guardband;

Maybe a small comment here to explain why we touch pipe_mode.
Eg.

/*
 * pipe_mode has already been derived from the
 * original adjusted_mode, keep the two in sync.
 */

Reviewed-by: Ville Syrjälä <[email protected]>

> +             pipe_mode->crtc_vblank_start =
> +                     adjusted_mode->crtc_vblank_start;
> +     }
> +
>       if (DISPLAY_VER(display) < 13)
>               crtc_state->vrr.pipeline_full =
>                       intel_vrr_guardband_to_pipeline_full(crtc_state,
> @@ -821,6 +829,19 @@ void intel_vrr_get_config(struct intel_crtc_state 
> *crtc_state)
>        */
>       if (crtc_state->vrr.enable)
>               crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
> +
> +     /*
> +      * For platforms that always use the VRR timing generator, we overwrite
> +      * crtc_vblank_start with vtotal - guardband to reflect the delayed
> +      * vblank start. This works for both default and optimized guardband 
> values.
> +      * On other platforms, we keep the original value from
> +      * intel_get_transcoder_timings() and apply adjustments only in 
> VRR-specific
> +      * paths as needed.
> +      */
> +     if (intel_vrr_always_use_vrr_tg(display))
> +             crtc_state->hw.adjusted_mode.crtc_vblank_start =
> +                     crtc_state->hw.adjusted_mode.crtc_vtotal -
> +                     crtc_state->vrr.guardband;
>  }
>  
>  int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state)
> -- 
> 2.45.2

-- 
Ville Syrjälä
Intel

Reply via email to