On Wed, Oct 15, 2025 at 12:15:15AM -0300, Gustavo Sousa wrote:
> When reading memory latencies for watermark calculations, previous
> display releases instructed to apply an adjustment of adding a certain
> value (e.g. 6us) to all levels when the level 0's memory latency read
> from hardware was zero.
>
> For Xe3p_LPD, the instruction is to always use 6us for level 0 and to
> add that value to the other levels. Update adjust_wm_latency()
> accordingly.
>
> Bspec: 68986, 69126
Reviewed-by: Matt Atwood <[email protected]>
> Signed-off-by: Gustavo Sousa <[email protected]>
> ---
> drivers/gpu/drm/i915/display/skl_watermark.c | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c
> b/drivers/gpu/drm/i915/display/skl_watermark.c
> index 41f64e347436..88342d07727f 100644
> --- a/drivers/gpu/drm/i915/display/skl_watermark.c
> +++ b/drivers/gpu/drm/i915/display/skl_watermark.c
> @@ -3249,6 +3249,13 @@ adjust_wm_latency(struct intel_display *display)
>
> make_wm_latency_monotonic(display);
>
> + /*
> + * Xe3p asks to ignore wm[0] read from the register and always
> + * use the adjustment done with read_latency.
> + */
> + if (DISPLAY_VER(display) >= 35)
> + wm[0] = 0;
> +
> /*
> * WaWmMemoryReadLatency
> *
>
> --
> 2.51.0
>
