On Wed, 01 Oct 2025, Mika Kahola <[email protected]> wrote: > From: Imre Deak <[email protected]> > > Factor out functions to begin and complete C10 PHY programming > sequences to make the code more concise.
access_begin and update_config don't sound like a matching pair, though. If you're reading code and see "access begin", I think you'd naturally expect to see a corresponding "access end/complete/commit/something", instead of "update config". > Signed-off-by: Imre Deak <[email protected]> > Signed-off-by: Mika Kahola <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 62 +++++++++++--------- > 1 file changed, 35 insertions(+), 27 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > index a74c1be225ac..9b38c7b4f0a7 100644 > --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c > @@ -449,6 +449,31 @@ static u8 intel_c10_get_tx_term_ctl(const struct > intel_crtc_state *crtc_state) > } > } > > +static void intel_c10_msgbus_access_begin(struct intel_encoder *encoder, > + u8 lane_mask) > +{ > + if (!intel_encoder_is_c10phy(encoder)) > + return; > + > + intel_cx0_rmw(encoder, lane_mask, PHY_C10_VDR_CONTROL(1), > + 0, C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED); > +} > + > +static void intel_c10_msgbus_update_config(struct intel_encoder *encoder, > + u8 lane_mask, bool master_lane) > +{ > + u8 val = C10_VDR_CTRL_UPDATE_CFG; > + > + if (!intel_encoder_is_c10phy(encoder)) > + return; > + > + if (master_lane) > + val |= C10_VDR_CTRL_MASTER_LANE; > + > + intel_cx0_rmw(encoder, lane_mask, PHY_C10_VDR_CONTROL(1), > + 0, val, MB_WRITE_COMMITTED); > +} > + > void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > { > @@ -472,9 +497,9 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder > *encoder, > return; > } > > + intel_c10_msgbus_access_begin(encoder, owned_lane_mask); > + > if (intel_encoder_is_c10phy(encoder)) { > - intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1), > - 0, C10_VDR_CTRL_MSGBUS_ACCESS, > MB_WRITE_COMMITTED); > intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CMN(3), > C10_CMN3_TXVBOOST_MASK, > > C10_CMN3_TXVBOOST(intel_c10_get_tx_vboost_lvl(crtc_state)), > @@ -513,9 +538,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder > *encoder, > 0, PHY_C10_VDR_OVRD_TX1 | PHY_C10_VDR_OVRD_TX2, > MB_WRITE_COMMITTED); > > - if (intel_encoder_is_c10phy(encoder)) > - intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1), > - 0, C10_VDR_CTRL_UPDATE_CFG, MB_WRITE_COMMITTED); > + intel_c10_msgbus_update_config(encoder, owned_lane_mask, false); > > intel_cx0_phy_transaction_end(encoder, wakeref); > } > @@ -2119,9 +2142,7 @@ static void intel_c10pll_readout_hw_state(struct > intel_encoder *encoder, > * According to C10 VDR Register programming Sequence we need > * to do this to read PHY internal registers from MsgBus. > */ > - intel_cx0_rmw(encoder, lane, PHY_C10_VDR_CONTROL(1), > - 0, C10_VDR_CTRL_MSGBUS_ACCESS, > - MB_WRITE_COMMITTED); > + intel_c10_msgbus_access_begin(encoder, lane); > > for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) > pll_state->pll[i] = intel_cx0_read(encoder, lane, > PHY_C10_VDR_PLL(i)); > @@ -2140,9 +2161,7 @@ static void intel_c10_pll_program(struct intel_display > *display, > { > int i; > > - intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CONTROL(1), > - 0, C10_VDR_CTRL_MSGBUS_ACCESS, > - MB_WRITE_COMMITTED); > + intel_c10_msgbus_access_begin(encoder, INTEL_CX0_BOTH_LANES); > > /* Program the pll values only for the master lane */ > for (i = 0; i < ARRAY_SIZE(pll_state->pll); i++) > @@ -2157,9 +2176,8 @@ static void intel_c10_pll_program(struct intel_display > *display, > intel_cx0_rmw(encoder, INTEL_CX0_BOTH_LANES, PHY_C10_VDR_CUSTOM_WIDTH, > C10_VDR_CUSTOM_WIDTH_MASK, C10_VDR_CUSTOM_WIDTH_8_10, > MB_WRITE_COMMITTED); > - intel_cx0_rmw(encoder, INTEL_CX0_LANE0, PHY_C10_VDR_CONTROL(1), > - 0, C10_VDR_CTRL_MASTER_LANE | C10_VDR_CTRL_UPDATE_CFG, > - MB_WRITE_COMMITTED); > + > + intel_c10_msgbus_update_config(encoder, INTEL_CX0_LANE0, true); > } > > static void intel_c10pll_dump_hw_state(struct intel_display *display, > @@ -2959,11 +2977,7 @@ static void intel_cx0_program_phy_lane(struct > intel_encoder *encoder, int lane_c > bool dp_alt_mode = > intel_tc_port_in_dp_alt_mode(enc_to_dig_port(encoder)); > u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder); > > - if (intel_encoder_is_c10phy(encoder)) > - intel_cx0_rmw(encoder, owned_lane_mask, > - PHY_C10_VDR_CONTROL(1), 0, > - C10_VDR_CTRL_MSGBUS_ACCESS, > - MB_WRITE_COMMITTED); > + intel_c10_msgbus_access_begin(encoder, owned_lane_mask); > > if (lane_reversal) > disables = REG_GENMASK8(3, 0) >> lane_count; > @@ -2988,11 +3002,7 @@ static void intel_cx0_program_phy_lane(struct > intel_encoder *encoder, int lane_c > MB_WRITE_COMMITTED); > } > > - if (intel_encoder_is_c10phy(encoder)) > - intel_cx0_rmw(encoder, owned_lane_mask, > - PHY_C10_VDR_CONTROL(1), 0, > - C10_VDR_CTRL_UPDATE_CFG, > - MB_WRITE_COMMITTED); > + intel_c10_msgbus_update_config(encoder, owned_lane_mask, false); > } > > static u32 intel_cx0_get_pclk_pll_request(u8 lane_mask) > @@ -3260,9 +3270,7 @@ void intel_lnl_mac_transmit_lfps(struct intel_encoder > *encoder, > > wakeref = intel_cx0_phy_transaction_begin(encoder); > > - if (intel_encoder_is_c10phy(encoder)) > - intel_cx0_rmw(encoder, owned_lane_mask, PHY_C10_VDR_CONTROL(1), > 0, > - C10_VDR_CTRL_MSGBUS_ACCESS, MB_WRITE_COMMITTED); > + intel_c10_msgbus_access_begin(encoder, owned_lane_mask); > > for (i = 0; i < 4; i++) { > int tx = i % 2 + 1; -- Jani Nikula, Intel
