On 15-10-2025 09:37, Suraj Kandpal wrote:
Program sequence from port clock ctl except for the SSC
enablement part which will be taken care of later.
Bspec: 74492
Signed-off-by: Suraj Kandpal <[email protected]>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 8 ++---
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 1 +
drivers/gpu/drm/i915/display/intel_lt_phy.c | 36 ++++++++++++++++++++
3 files changed, 41 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index db2b05521c62..eab49c08d7ff 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -2585,7 +2585,7 @@ static bool is_dp2(u32 clock)
return false;
}
-static bool is_hdmi_frl(u32 clock)
+bool intel_cx0_is_hdmi_frl(u32 clock)
{
switch (clock) {
case 300000: /* 3 Gbps */
@@ -2612,7 +2612,7 @@ static int intel_get_c20_custom_width(u32 clock, bool dp)
{
if (dp && is_dp2(clock))
return 2;
- else if (is_hdmi_frl(clock))
+ else if (intel_cx0_is_hdmi_frl(clock))
return 1;
else
return 0;
@@ -2706,7 +2706,7 @@ static void intel_c20_pll_program(struct intel_display
*display,
} else {
intel_cx0_rmw(encoder, owned_lane_mask,
PHY_C20_VDR_CUSTOM_SERDES_RATE,
BIT(7) | PHY_C20_CUSTOM_SERDES_MASK,
- is_hdmi_frl(port_clock) ? BIT(7) : 0,
+ intel_cx0_is_hdmi_frl(port_clock) ? BIT(7) : 0,
MB_WRITE_COMMITTED);
intel_cx0_write(encoder, INTEL_CX0_BOTH_LANES, PHY_C20_VDR_HDMI_RATE,
@@ -2766,7 +2766,7 @@ static void intel_program_port_clock_ctl(struct
intel_encoder *encoder,
val |= XELPDP_FORWARD_CLOCK_UNGATE;
- if (!is_dp && is_hdmi_frl(port_clock))
+ if (!is_dp && intel_cx0_is_hdmi_frl(port_clock))
Would it be better to move this to a different patch?
val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
else
val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index c92026fe7b8f..b111a893b428 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -43,6 +43,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder
*encoder,
const struct intel_crtc_state *crtc_state);
int intel_cx0_phy_check_hdmi_link_rate(struct intel_hdmi *hdmi, int clock);
void intel_cx0_setup_powerdown(struct intel_encoder *encoder);
+bool intel_cx0_is_hdmi_frl(u32 clock);
int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder);
void intel_cx0_pll_power_save_wa(struct intel_display *display);
void intel_lnl_mac_transmit_lfps(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/display/intel_lt_phy.c
b/drivers/gpu/drm/i915/display/intel_lt_phy.c
index c65333cc9494..8c6f60d9e0ac 100644
--- a/drivers/gpu/drm/i915/display/intel_lt_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_lt_phy.c
@@ -108,13 +108,49 @@ intel_lt_phy_lane_reset(struct intel_encoder *encoder,
intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
lane_phy_pulse_status, 0);
}
+static void
+intel_lt_phy_program_port_clock_ctl(struct intel_encoder *encoder,
+ const struct intel_crtc_state *crtc_state,
+ bool lane_reversal)
+{
+ struct intel_display *display = to_intel_display(encoder);
+ u32 val = 0;
+
+ intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),
+ XELPDP_PORT_REVERSAL,
+ lane_reversal ? XELPDP_PORT_REVERSAL : 0);
+
+ val |= XELPDP_FORWARD_CLOCK_UNGATE;
+
+ /*
+ * We actually mean MACCLK here and not MAXPCLK when using LT Phy
+ * but since the register bits still remain the same we use
+ * the same definition
+ */
+ if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) &&
+ intel_cx0_is_hdmi_frl(crtc_state->port_clock))
+ val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
XELPDP_DDI_CLOCK_SELECT_DIV18CLK);
+ else
+ val |= XELPDP_DDI_CLOCK_SELECT_PREP(display,
XELPDP_DDI_CLOCK_SELECT_MAXPCLK);
+
+ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
+ XELPDP_LANE1_PHY_CLOCK_SELECT |
XELPDP_FORWARD_CLOCK_UNGATE |
+ XELPDP_DDI_CLOCK_SELECT_MASK(display) |
XELPDP_SSC_ENABLE_PLLA |
+ XELPDP_SSC_ENABLE_PLLB, val);
+}
+
void intel_lt_phy_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
+ struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
+ bool lane_reversal = dig_port->lane_reversal;
+
/* 1. Enable MacCLK at default 162 MHz frequency. */
intel_lt_phy_lane_reset(encoder, crtc_state->lane_count);
/* 2. Program PORT_CLOCK_CTL register to configure clock muxes, gating, and SSC. */
+ intel_lt_phy_program_port_clock_ctl(encoder, crtc_state, lane_reversal);
+
/* 3. Change owned PHY lanes power to Ready state. */
/*
* 4. Read the PHY message bus VDR register PHY_VDR_0_Config check
enabled PLL type,
