Quoting Matt Roper (2025-10-22 14:58:05-03:00) >On Wed, Oct 22, 2025 at 03:28:26PM +0300, Ville Syrjälä wrote: >> On Tue, Oct 21, 2025 at 09:28:32PM -0300, Gustavo Sousa wrote: >> > From: Sai Teja Pottumuttu <[email protected]> >> > >> > Starting from display Xe3p_LPD, UINT16 formats are also supported. Add >> > its corresponding PLANE_CTL bit and add the format in the necessary >> > functions. >> >> Those have been supported by the hardware for a lot longer >> than that.
Yeah, Bspec shows that the support for UINT16 formats was already there before Xe3p_LPD. > >Agreed. General support was added back in ICL (bspec 7656), although it >appears that it was unofficial and not productized or fully >hardware-validated. It appears that support has remained unofficial >even up through these current platforms. So I'm not sure we really want >to enable this if we don't have a specific use case asking for it; it >will _probably_ work, but there may be corner cases that have problems >because it wasn't intended for real use. Yeah. I think I'll just drop the UINT16-related patches from this series. Thanks! -- Gustavo Sousa > >The only thing that seems to have changed is that UINT16 formats got >added to the list of formats that FBC can handle as part of the same >change that added the FP16 formats to that list. > > >Matt > >> >> I have an old branch that adds them here: >> https://github.com/vsyrjala/linux.git uint16 >> but I never landed that. >> >> > >> > v2: >> > - Add reference to Bspec 68911. (Matt Atwood) >> > >> > Bspec: 68904, 69853, 68911 >> > Signed-off-by: Sai Teja Pottumuttu <[email protected]> >> > Reviewed-by: Matt Atwood <[email protected]> >> > Signed-off-by: Gustavo Sousa <[email protected]> >> > --- >> > drivers/gpu/drm/i915/display/skl_universal_plane.c | 96 >> > +++++++++++++++------- >> > .../drm/i915/display/skl_universal_plane_regs.h | 1 + >> > 2 files changed, 68 insertions(+), 29 deletions(-) >> > >> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c >> > b/drivers/gpu/drm/i915/display/skl_universal_plane.c >> > index 0319174adf95..530adff81b99 100644 >> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c >> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c >> > @@ -136,36 +136,47 @@ static const u32 icl_sdr_uv_plane_formats[] = { >> > DRM_FORMAT_XVYU2101010, >> > }; >> > >> > +#define ICL_HDR_PLANE_FORMATS \ >> > + DRM_FORMAT_C8, \ >> > + DRM_FORMAT_RGB565, \ >> > + DRM_FORMAT_XRGB8888, \ >> > + DRM_FORMAT_XBGR8888, \ >> > + DRM_FORMAT_ARGB8888, \ >> > + DRM_FORMAT_ABGR8888, \ >> > + DRM_FORMAT_XRGB2101010, \ >> > + DRM_FORMAT_XBGR2101010, \ >> > + DRM_FORMAT_ARGB2101010, \ >> > + DRM_FORMAT_ABGR2101010, \ >> > + DRM_FORMAT_XRGB16161616F, \ >> > + DRM_FORMAT_XBGR16161616F, \ >> > + DRM_FORMAT_ARGB16161616F, \ >> > + DRM_FORMAT_ABGR16161616F, \ >> > + DRM_FORMAT_YUYV, \ >> > + DRM_FORMAT_YVYU, \ >> > + DRM_FORMAT_UYVY, \ >> > + DRM_FORMAT_VYUY, \ >> > + DRM_FORMAT_NV12, \ >> > + DRM_FORMAT_P010, \ >> > + DRM_FORMAT_P012, \ >> > + DRM_FORMAT_P016, \ >> > + DRM_FORMAT_Y210, \ >> > + DRM_FORMAT_Y212, \ >> > + DRM_FORMAT_Y216, \ >> > + DRM_FORMAT_XYUV8888, \ >> > + DRM_FORMAT_XVYU2101010, \ >> > + DRM_FORMAT_XVYU12_16161616, \ >> > + DRM_FORMAT_XVYU16161616 >> > + >> > static const u32 icl_hdr_plane_formats[] = { >> > - DRM_FORMAT_C8, >> > - DRM_FORMAT_RGB565, >> > - DRM_FORMAT_XRGB8888, >> > - DRM_FORMAT_XBGR8888, >> > - DRM_FORMAT_ARGB8888, >> > - DRM_FORMAT_ABGR8888, >> > - DRM_FORMAT_XRGB2101010, >> > - DRM_FORMAT_XBGR2101010, >> > - DRM_FORMAT_ARGB2101010, >> > - DRM_FORMAT_ABGR2101010, >> > - DRM_FORMAT_XRGB16161616F, >> > - DRM_FORMAT_XBGR16161616F, >> > - DRM_FORMAT_ARGB16161616F, >> > - DRM_FORMAT_ABGR16161616F, >> > - DRM_FORMAT_YUYV, >> > - DRM_FORMAT_YVYU, >> > - DRM_FORMAT_UYVY, >> > - DRM_FORMAT_VYUY, >> > - DRM_FORMAT_NV12, >> > - DRM_FORMAT_P010, >> > - DRM_FORMAT_P012, >> > - DRM_FORMAT_P016, >> > - DRM_FORMAT_Y210, >> > - DRM_FORMAT_Y212, >> > - DRM_FORMAT_Y216, >> > - DRM_FORMAT_XYUV8888, >> > - DRM_FORMAT_XVYU2101010, >> > - DRM_FORMAT_XVYU12_16161616, >> > - DRM_FORMAT_XVYU16161616, >> > + ICL_HDR_PLANE_FORMATS, >> > +}; >> > + >> > +static const u32 xe3p_lpd_hdr_plane_formats[] = { >> > + ICL_HDR_PLANE_FORMATS, >> > + DRM_FORMAT_XRGB16161616, >> > + DRM_FORMAT_XBGR16161616, >> > + DRM_FORMAT_ARGB16161616, >> > + DRM_FORMAT_ABGR16161616, >> > }; >> > >> > int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) >> > @@ -220,6 +231,18 @@ int skl_format_to_fourcc(int format, bool rgb_order, >> > bool alpha) >> > else >> > return DRM_FORMAT_XRGB2101010; >> > } >> > + case PLANE_CTL_FORMAT_XRGB_16161616: >> > + if (rgb_order) { >> > + if (alpha) >> > + return DRM_FORMAT_ABGR16161616; >> > + else >> > + return DRM_FORMAT_XBGR16161616; >> > + } else { >> > + if (alpha) >> > + return DRM_FORMAT_ARGB16161616; >> > + else >> > + return DRM_FORMAT_XRGB16161616; >> > + } >> > case PLANE_CTL_FORMAT_XRGB_16161616F: >> > if (rgb_order) { >> > if (alpha) >> > @@ -960,6 +983,12 @@ static u32 skl_plane_ctl_format(u32 pixel_format) >> > case DRM_FORMAT_XRGB2101010: >> > case DRM_FORMAT_ARGB2101010: >> > return PLANE_CTL_FORMAT_XRGB_2101010; >> > + case DRM_FORMAT_XBGR16161616: >> > + case DRM_FORMAT_ABGR16161616: >> > + return PLANE_CTL_FORMAT_XRGB_16161616 | >> > PLANE_CTL_ORDER_RGBX; >> > + case DRM_FORMAT_XRGB16161616: >> > + case DRM_FORMAT_ARGB16161616: >> > + return PLANE_CTL_FORMAT_XRGB_16161616; >> > case DRM_FORMAT_XBGR16161616F: >> > case DRM_FORMAT_ABGR16161616F: >> > return PLANE_CTL_FORMAT_XRGB_16161616F | >> > PLANE_CTL_ORDER_RGBX; >> > @@ -2479,6 +2508,11 @@ static const u32 *icl_get_plane_formats(struct >> > intel_display *display, >> > int *num_formats) >> > { >> > if (icl_is_hdr_plane(display, plane_id)) { >> > + if (DISPLAY_VER(display) >= 35) { >> > + *num_formats = >> > ARRAY_SIZE(xe3p_lpd_hdr_plane_formats); >> > + return xe3p_lpd_hdr_plane_formats; >> > + } >> > + >> > *num_formats = ARRAY_SIZE(icl_hdr_plane_formats); >> > return icl_hdr_plane_formats; >> > } else if (icl_is_nv12_y_plane(display, plane_id)) { >> > @@ -2637,6 +2671,10 @@ static bool tgl_plane_format_mod_supported(struct >> > drm_plane *_plane, >> > case DRM_FORMAT_RGB565: >> > case DRM_FORMAT_XVYU2101010: >> > case DRM_FORMAT_C8: >> > + case DRM_FORMAT_XBGR16161616: >> > + case DRM_FORMAT_ABGR16161616: >> > + case DRM_FORMAT_XRGB16161616: >> > + case DRM_FORMAT_ARGB16161616: >> > case DRM_FORMAT_Y210: >> > case DRM_FORMAT_Y212: >> > case DRM_FORMAT_Y216: >> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h >> > b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h >> > index 479bb3f7f92b..84cf565bd653 100644 >> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h >> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane_regs.h >> > @@ -64,6 +64,7 @@ >> > #define PLANE_CTL_FORMAT_Y410 >> > REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 7) >> > #define PLANE_CTL_FORMAT_Y412 >> > REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 9) >> > #define PLANE_CTL_FORMAT_Y416 >> > REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 11) >> > +#define PLANE_CTL_FORMAT_XRGB_16161616 >> > REG_FIELD_PREP(PLANE_CTL_FORMAT_MASK_ICL, 18) >> > #define PLANE_CTL_PIPE_CSC_ENABLE REG_BIT(23) /* Pre-GLK >> > */ >> > #define PLANE_CTL_KEY_ENABLE_MASK REG_GENMASK(22, 21) >> > #define PLANE_CTL_KEY_ENABLE_SOURCE >> > REG_FIELD_PREP(PLANE_CTL_KEY_ENABLE_MASK, 1) >> > >> > -- >> > 2.51.0 >> >> -- >> Ville Syrjälä >> Intel > >-- >Matt Roper >Graphics Software Engineer >Linux GPU Platform Enablement >Intel Corporation
