On Tue, Oct 28, 2025 at 11:36:18AM +0200, Juha-Pekka Heikkilä wrote: > Set is > > Reviewed-by: Juha-Pekka Heikkila <[email protected]> > > Only thing I was wondering about is that cbcr handling with that plane > min width but I assume you've tested it works as we're not getting > much of ci results for these.
The actual limits aren't changing here so not much to test in that sense. I've never actually tested to see what happens if the plane is below that w/a min width, but IIRC from reading the hsd the problem was more along the linds of extra power draw rather than underrun/etc. > > /Juha-Pekka > > On Fri, Oct 10, 2025 at 12:13 AM Ville Syrjala > <[email protected]> wrote: > > > > From: Ville Syrjälä <[email protected]> > > > > Fix up some of the universal plane min size handling, and do > > a bit of random cleanup. > > > > Ville Syrjälä (8): > > drm/i915: Rewrite icl_min_plane_width() > > drm/i915: Drop the min plane width w/a adl+ > > drm/i915: Implement .min_plane_width() for PTL+ > > drm/i915: Start checking plane min size for the chroma plane > > drm/i915: Introduce intel_plane_min_height() > > drm/i915: Remove pointless crtc hw.enable check > > drm/i915: Extract glk_plane_has_planar() > > drm/i915: Unify the logic in {skl,glk}_plane_has_*() > > > > .../drm/i915/display/skl_universal_plane.c | 94 +++++++++---------- > > 1 file changed, 44 insertions(+), 50 deletions(-) > > > > -- > > 2.49.1 > > -- Ville Syrjälä Intel
