On Thu, Oct 30, 2025 at 10:47:51AM +0530, Ankit Nautiyal wrote:
> Correct the bit-shift logic to properly readback the 10 bit target_rr from
> DB3 and DB4.
>
> Fixes: 12ea89291603 ("drm/i915/dp: Add Read/Write support for Adaptive Sync
> SDP")
> Cc: Mitul Golani <[email protected]>
> Cc: Ankit Nautiyal <[email protected]>
> Signed-off-by: Ankit Nautiyal <[email protected]>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index 475518b4048b..c013eb2e18a1 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -4996,7 +4996,7 @@ int intel_dp_as_sdp_unpack(struct drm_dp_as_sdp *as_sdp,
> as_sdp->length = sdp->sdp_header.HB3 & DP_ADAPTIVE_SYNC_SDP_LENGTH;
> as_sdp->mode = sdp->db[0] & DP_ADAPTIVE_SYNC_SDP_OPERATION_MODE;
> as_sdp->vtotal = (sdp->db[2] << 8) | sdp->db[1];
> - as_sdp->target_rr = (u64)sdp->db[3] | ((u64)sdp->db[4] & 0x3);
> + as_sdp->target_rr = (u64)sdp->db[3] | ((u64)(sdp->db[4] & 0x3) << 8);
The (u64) casts are completely pointless. And I would try to write this
in a styple that is more consistent with the vtotal assignment right
above it. Eg.: target_rr = ((db[4] & 0x3) << 8) | db[3];
> as_sdp->target_rr_divider = sdp->db[4] & 0x20 ? true : false;
>
> return 0;
> --
> 2.45.2
--
Ville Syrjälä
Intel
