This series adds initial support for Xe3p_LPD, Intel's display architecture with IP version 35.
This series contains basic enabling patches and does not provide complete support for the display IP yet. More involved features, like the new PHY implementation and ALPM are implemented as separate patch series. Signed-off-by: Gustavo Sousa <[email protected]> --- Changes in v3: - Reshuffled patches so that most of the ones already containing a r-b are placed at the start. - Dropped "drm/i915/xe3p_lpd: Wait for AUX channel power status", as a similar patch was already applied from a patch series dedicated to LT PHY (https://lore.kernel.org/all/[email protected]/). - Dropped patches related to UINT16 plane formats, as they were incomplete and were not specific to Xe3p_LPD. - Dropped FBC related patches, as Vinod is handling them as a separated series (https://lore.kernel.org/intel-gfx/[email protected]/) - Dropped "drm/i915/xe3p_lpd: PSR SU minimum lines is 4", since that change is not valid according to Bspec. - Incorporated review feedback on the other patches. Please check the changelog in the individual patches for details. - Link to v2: https://lore.kernel.org/r/[email protected] Changes in v2: - Incorporated review feedback. Please check the changelog in the patches for details. - Link to v1: https://lore.kernel.org/r/[email protected] --- Ankit Nautiyal (1): drm/i915/xe3p_lpd: Drop support for interlace mode Gustavo Sousa (16): drm/i915/display: Use braces for if-ladder in intel_bw_init_hw() drm/i915/xe3p_lpd: Add CDCLK table drm/i915/xe3p_lpd: Load DMC firmware drm/i915/xe3p_lpd: Extend Wa_16025573575 drm/i915/xe3p_lpd: Reload DMC MMIO for pipes C and D drm/i915/dram: Add field ecc_impacting_de_bw drm/i915/xe3p_lpd: Log FBC-related debug info for PIPE underrun drm/i915/wm: Do not make latency values monotonic on Xe3 onward drm/i915/xe3p_lpd: Always apply WaWmMemoryReadLatency drm/i915/vbt: Add fields dedicated_external and dyn_port_over_tc drm/i915/power: Use intel_encoder_is_tc() drm/i915/display: Handle dedicated external ports in intel_encoder_is_tc() drm/i915/xe3p_lpd: Extend Type-C flow for static DDI allocation drm/i915/display: Use platform check in HAS_LT_PHY() drm/i915/display: Move HAS_LT_PHY() to intel_display_device.h drm/i915/display: Use HAS_LT_PHY() for LT PHY AUX power Juha-pekka Heikkila (1): drm/i915/xe3p_lpd: Don't allow odd ypan or ysize with semiplanar format Luca Coelho (1): drm/i915/wm: don't use method1 in Xe3p_LPD onwards Matt Atwood (1): drm/i915/xe3p_lpd: Update bandwidth parameters Matt Roper (1): drm/i915/xe3p_lpd: Drop north display reset option programming Ravi Kumar Vodapalli (1): drm/i915/xe3p_lpd: Adapt to updates on MBUS_CTL/DBUF_CTL registers Sai Teja Pottumuttu (6): drm/i915/xe3p_lpd: Add Xe3p_LPD display IP features drm/i915/xe3p_lpd: Expand bifield masks dbuf blocks fields drm/i915/xe3p_lpd: Horizontal flip support for linear surfaces drm/i915/xe3p_lpd: Remove gamma,csc bottom color checks drm/i915/xe3p_lpd: Underrun debuggability and error codes/hints drm/i915/nvls: Add NVL-S display support Vinod Govindapillai (1): drm/i915/xe3p_lpd: Enable system caching for FBC drivers/gpu/drm/i915/display/intel_bios.c | 54 +++++++- drivers/gpu/drm/i915/display/intel_bios.h | 2 + drivers/gpu/drm/i915/display/intel_bw.c | 43 +++--- drivers/gpu/drm/i915/display/intel_cdclk.c | 44 +++++- drivers/gpu/drm/i915/display/intel_color.c | 13 +- drivers/gpu/drm/i915/display/intel_ddi.c | 11 ++ drivers/gpu/drm/i915/display/intel_display.c | 33 ++++- .../gpu/drm/i915/display/intel_display_device.c | 6 + .../gpu/drm/i915/display/intel_display_device.h | 5 +- drivers/gpu/drm/i915/display/intel_display_power.c | 3 + .../drm/i915/display/intel_display_power_well.c | 42 +++--- drivers/gpu/drm/i915/display/intel_display_regs.h | 40 +++++- drivers/gpu/drm/i915/display/intel_display_types.h | 1 + drivers/gpu/drm/i915/display/intel_display_wa.c | 3 +- drivers/gpu/drm/i915/display/intel_dmc.c | 13 +- drivers/gpu/drm/i915/display/intel_fbc.c | 92 +++++++++++++ drivers/gpu/drm/i915/display/intel_fbc.h | 2 + drivers/gpu/drm/i915/display/intel_fbc_regs.h | 11 ++ drivers/gpu/drm/i915/display/intel_fifo_underrun.c | 73 ++++++++++ drivers/gpu/drm/i915/display/intel_lt_phy.h | 2 - drivers/gpu/drm/i915/display/intel_plane.c | 3 + drivers/gpu/drm/i915/display/intel_tc.c | 151 ++++++++++++++++++++- drivers/gpu/drm/i915/display/intel_vbt_defs.h | 3 +- drivers/gpu/drm/i915/display/skl_universal_plane.c | 3 +- .../drm/i915/display/skl_universal_plane_regs.h | 12 +- drivers/gpu/drm/i915/display/skl_watermark.c | 42 +++++- drivers/gpu/drm/i915/display/skl_watermark_regs.h | 52 +++---- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/soc/intel_dram.c | 4 + drivers/gpu/drm/i915/soc/intel_dram.h | 1 + 30 files changed, 670 insertions(+), 95 deletions(-) --- base-commit: c6cd36e5d63bd95a7b68e934d874921a67aecfd2 change-id: 20251014-xe3p_lpd-basic-enabling-eb4424698b44 Best regards, -- Gustavo Sousa <[email protected]>
