Add function to check if DC Balance possibile on requested PIPE and also validate along with DISPLAY_VER check.
Signed-off-by: Mitul Golani <[email protected]> Reviewed-by: Ankit Nautiyal <[email protected]> --- drivers/gpu/drm/i915/display/intel_vrr.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c index 87945b031a7d..8aba20a50d92 100644 --- a/drivers/gpu/drm/i915/display/intel_vrr.c +++ b/drivers/gpu/drm/i915/display/intel_vrr.c @@ -263,11 +263,25 @@ void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state) } static -void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state, - int vmin, int vmax) +int intel_vrr_dc_balance_possible(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + enum pipe pipe = crtc->pipe; + + /* + * FIXME: Currently Firmware supports DC Balancing on PIPE A + * and PIPE B. Account those limitation while computing DC + * Balance parameters. + */ + return (HAS_VRR_DC_BALANCE(display) && + ((pipe == PIPE_A) || (pipe == PIPE_B))); +} +static +void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state, + int vmin, int vmax) +{ crtc_state->vrr.vmax = vmax; crtc_state->vrr.vmin = vmin; crtc_state->vrr.flipline = crtc_state->vrr.vmin; @@ -275,7 +289,7 @@ void intel_vrr_compute_vrr_timings(struct intel_crtc_state *crtc_state, crtc_state->vrr.enable = true; crtc_state->mode_flags |= I915_MODE_FLAG_VRR; - if (HAS_VRR_DC_BALANCE(display)) + if (intel_vrr_dc_balance_possible(crtc_state)) crtc_state->vrr.dc_balance.enable = true; } -- 2.48.1
