PSR2_MAN_TRK_CTL[SF Continuous full frame] is sampled on the rising edge of delayed vblank. SW must ensure this bit is not changing around that bit. Due to this PSR2 Selective Fetch needs vblank evasion.
Due to this add helper for intel_pipe_update_start usage to choose if vblank evasion is needed by PSR. Bspec: 50424 Signed-off-by: Jouni Högander <[email protected]> --- drivers/gpu/drm/i915/display/intel_psr.c | 15 +++++++++++++++ drivers/gpu/drm/i915/display/intel_psr.h | 1 + 2 files changed, 16 insertions(+) diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 08bca4573974..18d5fe992f58 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -4540,3 +4540,18 @@ int intel_psr_min_guardband(struct intel_crtc_state *crtc_state) return psr_min_guardband; } + +bool intel_psr_needs_evasion(const struct intel_crtc_state *crtc_state) +{ + struct intel_display *display = to_intel_display(crtc_state); + struct intel_encoder *encoder; + struct intel_dp *intel_dp; + + for_each_intel_encoder_mask_with_psr(display->drm, encoder, + crtc_state->uapi.encoder_mask) { + intel_dp = enc_to_intel_dp(encoder); + + break; + } + return intel_dp->psr.psr2_sel_fetch_enabled; +} diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h index 620b35928832..8c09a9f8a00e 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.h +++ b/drivers/gpu/drm/i915/display/intel_psr.h @@ -86,5 +86,6 @@ bool intel_psr_needs_alpm_aux_less(struct intel_dp *intel_dp, void intel_psr_compute_config_late(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state); int intel_psr_min_guardband(struct intel_crtc_state *crtc_state); +bool intel_psr_needs_evasion(const struct intel_crtc_state *crtc_state); #endif /* __INTEL_PSR_H__ */ -- 2.43.0
