Re: [PATCH v9 10/17] drm/i915/vrr: Write DC balance params to hw registers

[Nautiyal, Ankit K]

On 11/27/2025 2:46 PM, Mitul Golani wrote:

Write DC Balance parameters to hw registers.

--v2:
- Update commit header.
- Separate crtc_state params from this patch. (Ankit)

--v3:
- Write registers at compute config.
- Update condition for write.

--v4:
- Address issue with state checker.

--v5:
- Initialise some more dc balance register while enabling VRR.

--v6:
- FLIPLINE_CFG need to be configure at last, as it is double buffer
arming point.

--v7:
- Initialise and reset live value of vmax and vmin as well.

--v8:
- Add separate functions while writing hw registers. (Ankit)

--v9:
- Add DC Balance counter enable bit to this patch. (Ankit)

--v10:
- Add rigister writes to vrr_enable/disable. (Ankit)

Signed-off-by: Mitul Golani <mitulkumar.ajitkumar.gol...@intel.com>

Reviewed-by: Ankit Nautiyal <ankit.k.nauti...@intel.com>

---
  drivers/gpu/drm/i915/display/intel_vrr.c | 76 ++++++++++++++++++++++++
  1 file changed, 76 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c 
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 411ae5da3824..11f06a5b854a 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -767,6 +767,80 @@ static void intel_vrr_set_vrr_timings(const struct 
intel_crtc_state *crtc_state)
                       intel_vrr_hw_flipline(crtc_state) - 1);
  }

+static void

+intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state)
+{
+       struct intel_display *display = to_intel_display(crtc_state);
+       enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+       struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+       enum pipe pipe = crtc->pipe;
+
+       if (!crtc_state->vrr.dc_balance.enable)
+               return;
+
+       intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder),
+                      VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1));
+       intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder),
+                      VRR_DCB_ADJ_VMAX(crtc_state->vrr.vmax - 1));
+       intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder),
+                      VRR_DCB_VMAX(crtc_state->vrr.vmax - 1));
+       intel_de_write(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder),
+                      VRR_DCB_VMAX(crtc_state->vrr.vmax - 1));
+       intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder),
+                      VRR_DCB_FLIPLINE(crtc_state->vrr.flipline - 1));
+       intel_de_write(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder),
+                      VRR_DCB_FLIPLINE(crtc_state->vrr.flipline - 1));
+       intel_de_write(display, 
TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder),
+                      VRR_DCB_ADJ_FLIPLINE(crtc_state->vrr.flipline - 1));
+       intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder),
+                      VRR_DCB_ADJ_FLIPLINE(crtc_state->vrr.flipline - 1));
+       intel_de_write(display, PIPEDMC_DCB_VMIN(pipe),
+                      crtc_state->vrr.dc_balance.vmin - 1);
+       intel_de_write(display, PIPEDMC_DCB_VMAX(pipe),
+                      crtc_state->vrr.dc_balance.vmax - 1);
+       intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe),
+                      crtc_state->vrr.dc_balance.max_increase);
+       intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe),
+                      crtc_state->vrr.dc_balance.max_decrease);
+       intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe),
+                      crtc_state->vrr.dc_balance.guardband);
+       intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe),
+                      crtc_state->vrr.dc_balance.slope);
+       intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe),
+                      crtc_state->vrr.dc_balance.vblank_target);
+       intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder),
+                      ADAPTIVE_SYNC_COUNTER_EN);
+}
+
+static void
+intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
+{
+       struct intel_display *display = to_intel_display(old_crtc_state);
+       enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
+       struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+       enum pipe pipe = crtc->pipe;
+
+       if (!old_crtc_state->vrr.dc_balance.enable)
+               return;
+
+       intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0);
+       intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0);
+       intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);
+       intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe), 0);
+       intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe), 0);
+       intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe), 0);
+       intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe), 0);
+       intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe), 0);
+       intel_de_write(display, 
TRANS_VRR_DCB_ADJ_VMAX_CFG_LIVE(cpu_transcoder), 0);
+       intel_de_write(display, 
TRANS_VRR_DCB_ADJ_FLIPLINE_CFG_LIVE(cpu_transcoder), 0);
+       intel_de_write(display, TRANS_VRR_DCB_VMAX_LIVE(cpu_transcoder), 0);
+       intel_de_write(display, TRANS_VRR_DCB_FLIPLINE_LIVE(cpu_transcoder), 0);
+       intel_de_write(display, TRANS_VRR_DCB_ADJ_VMAX_CFG(cpu_transcoder), 0);
+       intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), 
0);
+       intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), 0);
+       intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder), 0);
+}
+
  static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
                                bool cmrr_enable)
  {
@@ -813,6 +887,7 @@ void intel_vrr_enable(const struct intel_crtc_state 
*crtc_state)
                return;

intel_vrr_set_vrr_timings(crtc_state);

+       intel_vrr_enable_dc_balancing(crtc_state);

if (!intel_vrr_always_use_vrr_tg(display))

                intel_vrr_tg_enable(crtc_state, crtc_state->cmrr.enable);
@@ -828,6 +903,7 @@ void intel_vrr_disable(const struct intel_crtc_state 
*old_crtc_state)
        if (!intel_vrr_always_use_vrr_tg(display))
                intel_vrr_tg_disable(old_crtc_state);

+ intel_vrr_disable_dc_balancing(old_crtc_state);

        intel_vrr_set_fixed_rr_timings(old_crtc_state);
  }