Hey, Den 2025-11-26 kl. 20:56, skrev Shankar, Uma: > > >> -----Original Message----- >> From: Ville Syrjälä <[email protected]> >> Sent: Thursday, November 27, 2025 1:13 AM >> To: Shankar, Uma <[email protected]> >> Cc: Maarten Lankhorst <[email protected]>; [email protected]; >> [email protected]; [email protected]; Mario Kleiner >> <[email protected]>; Mike Galbraith <[email protected]>; >> Thomas Gleixner <[email protected]>; Sebastian Andrzej Siewior >> <[email protected]>; Clark Williams <[email protected]>; Steven >> Rostedt <[email protected]> >> Subject: Re: [PATCH v2 2/7] drm/i915/display: Use intel_de_write_fw in >> intel_pipe_fastset >> >> On Wed, Nov 26, 2025 at 07:19:47PM +0000, Shankar, Uma wrote: >>> >>> >>>> -----Original Message----- >>>> From: Intel-gfx <[email protected]> On Behalf >>>> Of Maarten Lankhorst >>>> Sent: Tuesday, November 4, 2025 2:06 PM >>>> To: [email protected]; [email protected] >>>> Cc: [email protected]; Maarten Lankhorst >>>> <[email protected]>; Mario Kleiner <[email protected]>; Mike >>>> Galbraith <[email protected]>; Thomas Gleixner >>>> <[email protected]>; Sebastian Andrzej Siewior >>>> <[email protected]>; Clark Williams <[email protected]>; >>>> Steven Rostedt <[email protected]> >>>> Subject: [PATCH v2 2/7] drm/i915/display: Use intel_de_write_fw in >>>> intel_pipe_fastset >>>> >>>> intel_set_pipe_src_size(), hsw_set_linetime_wm(), >>>> intel_cpu_transcoder_set_m1_n1() and >>>> intel_set_transcoder_timings_lrr() >>>> are called from an atomic context on PREEMPT_RT, and should be using >>>> the _fw functions. >>> >>> This could be ok but we need to be sure that all are called with power >>> domains >> up. >>> I think would be safe to keep this under RT check so that we don't end >>> up breaking any generic non RT usecase. >> >> When removing the locks from register accesses one needs to consider what >> platforms the code runs on, what other register are on the same cacheline, >> and >> whether they can be accessed in parallel. If there is something there then >> we may >> not be able to remove the locks. >> >> That's assuming the "system hangs when same cacheline is accessed from >> multiple cpus" issue is real for display registers, and I'm actually not >> 100% it is. >> But we'd need to run some tests on the affected systems >> (~ivb/hsw) to get any kind of confidence here. IIRC some old intel_gpu_top >> thhat >> directly poked the registers was very good at hitting it on hsw at least, so >> that >> would be a decent starting point. >> >> Anyways, I'm going to be replacing the uncore lock with a display specific >> lock >> soonish, and I suppose I can just make that a raw spinlock to appease RT. > > Thanks Ville, yeah I am also not confident to switch to the fw version. Even > if we have > to try this should be made limited to RT cases, where we can contain and > stabilize as > we test and find out any issues. > Direct poking of registers requires root privileges, so that should not be > something we have to worry about. It's not something required by any driver.
The specific calls are called during modeset, fastset and pageflip, and by design there is no chance of those racing with each other. They're serialized between each other. Kind regards, ~Maarten Lankhorst
