From: Ville Syrjälä <[email protected]> Use the proper IS0_R name for the VGA input status register 0, instead of using the VGA_MIS_W alias which is meant for write accesses to the same address. Yes, VGA registers are weird.
Signed-off-by: Ville Syrjälä <[email protected]> --- drivers/gpu/drm/i915/display/intel_crt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c index dedc26f6a2b2..6f216ba887bc 100644 --- a/drivers/gpu/drm/i915/display/intel_crt.c +++ b/drivers/gpu/drm/i915/display/intel_crt.c @@ -738,7 +738,7 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe) * border color for Color info. */ intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe)); - st00 = intel_vga_read(display, VGA_MIS_W, true); + st00 = intel_vga_read(display, VGA_IS0_R, true); status = ((st00 & (1 << 4)) != 0) ? connector_status_connected : connector_status_disconnected; @@ -786,7 +786,7 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe) do { count++; /* Read the ST00 VGA status register */ - st00 = intel_vga_read(display, VGA_MIS_W, true); + st00 = intel_vga_read(display, VGA_IS0_R, true); if (st00 & (1 << 4)) detect++; } while ((intel_de_read(display, PIPEDSL(display, pipe)) == dsl)); -- 2.51.2
