On Mon, 08 Dec 2025, Ville Syrjala <[email protected]> wrote: > From: Ville Syrjälä <[email protected]> > > We want out VGA register accesses to land on the correct GPU.
our? > Check that the VGA routing is appropriately configured. > > For the iGPU this just means the IO decode enable on the GPU, but > for dGPUs we also need the entire chain of bridges to forward the > VGA accesses. > > Signed-off-by: Ville Syrjälä <[email protected]> Acked-by: Jani Nikula <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_vga.c | 24 ++++++++++++++++++++++++ > 1 file changed, 24 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_vga.c > b/drivers/gpu/drm/i915/display/intel_vga.c > index f2f7d396c556..e51451966f72 100644 > --- a/drivers/gpu/drm/i915/display/intel_vga.c > +++ b/drivers/gpu/drm/i915/display/intel_vga.c > @@ -58,6 +58,28 @@ static bool has_vga_pipe_sel(struct intel_display *display) > return DISPLAY_VER(display) < 7; > } > > +static bool intel_pci_has_vga_io_decode(struct pci_dev *pdev) > +{ > + u16 cmd = 0; > + > + pci_read_config_word(pdev, PCI_COMMAND, &cmd); > + if ((cmd & PCI_COMMAND_IO) == 0) > + return false; > + > + pdev = pdev->bus->self; > + while (pdev) { > + u16 ctl = 0; > + > + pci_read_config_word(pdev, PCI_BRIDGE_CONTROL, &ctl); > + if ((ctl & PCI_BRIDGE_CTL_VGA) == 0) > + return false; > + > + pdev = pdev->bus->self; > + } > + > + return true; > +} > + > static bool intel_pci_set_io_decode(struct pci_dev *pdev, bool enable) > { > u16 old = 0, cmd; > @@ -169,6 +191,8 @@ void intel_vga_disable(struct intel_display *display) > > io_decode = intel_vga_get(display); > > + drm_WARN_ON(display->drm, !intel_pci_has_vga_io_decode(pdev)); > + > outb(0x01, VGA_SEQ_I); > sr1 = inb(VGA_SEQ_D); > outb(sr1 | VGA_SR01_SCREEN_OFF, VGA_SEQ_D); -- Jani Nikula, Intel
