Add explicit port clock validation and simplify PLL state handling by
removing redundant cached clock data. The series improves robustness of
PLL divider handling, particularly for algorithmically derived clocks,
and makes port clock usage more consistent across the driver.
The driver derives port clocks from PLL divider configuration but does
not consistently verify that the calculated clock matches the requested
one. This is especially relevant for HDMI non-FRL modes, where PLL
dividers are selected algorithmically rather than via fixed mappings.
Introduce a fuzzy port clock check to compare calculated and requested
values within a small tolerance, and warn when mismatches are detected.
This allows early detection of invalid or unintended divider solutions
without changing functional behavior.
The PLL state currently caches a `.clock` value even though the port
clock is fully derivable from the divider configuration. Keeping this
cached value is redundant and risks divergence from the actual computed
clock. Remove `.clock` and convert all users to rely on on-demand
port clock calculation instead.
This series:
- Introduces helper functions for port clock calculation with clear
inputs, outputs, and units.
- Adds a centralized fuzzy port-clock sanity check (±2 kHz tolerance)
applied during boot and mode-setting.
- Moves scattered port-clock calculations into common helpers.
- Removes the `.clock` member from PLL state structures.
Mika Kahola (13):
drm/i915/c10: Move C10 port clock calculation
drm/i915/c20: Move C20 port clock calculation
drm/i915/display: Drop crtc_state from clock calculation
drm/i915/cx0: Fix HDMI FRL clock rates
drm/i915/cx0: Create macro around pll tables
drm/i915/lt_phy: Create macro for lt phy pll state
drm/i915/display: Add helper function for fuzzy clock check
drm/i915/cx0: Replace encoder with display
drm/i915/cx0: Verify C10/C20 pll dividers
drm/i915/lt_phy: Add verfication for lt phy pll dividers
drm/i915/cx0: Drop C20 25.175 MHz rate
drm/i915/lt_phy: Drop 27.2 MHz rate
drm/i915/display: Remove .clock member from eDP/DP/HDMI pll tables
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 749 ++++++++++--------
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 3 +
drivers/gpu/drm/i915/display/intel_ddi.c | 4 +-
drivers/gpu/drm/i915/display/intel_dpll.c | 3 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 13 +-
drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 3 -
drivers/gpu/drm/i915/display/intel_lt_phy.c | 238 +++---
drivers/gpu/drm/i915/display/intel_lt_phy.h | 5 +-
.../drm/i915/display/intel_snps_hdmi_pll.c | 3 -
9 files changed, 539 insertions(+), 482 deletions(-)
--
2.34.1
