This is the second part of patchset [1] containing the refactoring (patches 13-15, 20-35) of the link BW computation to simplify it. The first part of [1] containing fixes is merged now to drm-tip, see [2], the third part of [1] refactoring the DSC slice computation is to be sent as a follow-up to this patchset.
[1] https://lore.kernel.org/all/[email protected] [2] https://lore.kernel.org/all/[email protected] Cc: Ankit Nautiyal <[email protected]> Cc: Luca Coelho <[email protected]> Cc: Jouni Högander <[email protected]> Cc: Vinod Govindapillai <[email protected]> Imre Deak (19): drm/i915/dp: Drop unused timeslots param from dsc_compute_link_config() drm/i915/dp: Factor out align_max_sink_dsc_input_bpp() drm/i915/dp: Factor out align_max_vesa_compressed_bpp_x16() drm/i915/dp: Align min/max DSC input BPPs to sink caps drm/i915/dp: Align min/max compressed BPPs when calculating BPP limits drm/i915/dp: Drop intel_dp parameter from intel_dp_compute_config_link_bpp_limits() drm/i915/dp: Pass intel_output_format to intel_dp_dsc_sink_{min_max}_compressed_bpp() drm/i915/dp: Pass mode clock to dsc_throughput_quirk_max_bpp_x16() drm/i915/dp: Factor out compute_min_compressed_bpp_x16() drm/i915/dp: Factor out compute_max_compressed_bpp_x16() drm/i915/dp: Add intel_dp_mode_valid_with_dsc() drm/i915/dp: Unify detect and compute time DSC mode BW validation drm/i915/dp: Use helpers to align min/max compressed BPPs drm/i915/dp: Simplify computing DSC BPPs for eDP drm/i915/dp: Simplify computing DSC BPPs for DP-SST drm/i915/dp: Simplify computing forced DSC BPP for DP-SST drm/i915/dp: Unify computing compressed BPP for DP-SST and eDP drm/i915/dp: Simplify eDP vs. DP compressed BPP computation drm/i915/dp: Simplify computing the DSC compressed BPP for DP-MST drivers/gpu/drm/i915/display/intel_dp.c | 515 +++++++++----------- drivers/gpu/drm/i915/display/intel_dp.h | 17 +- drivers/gpu/drm/i915/display/intel_dp_mst.c | 77 +-- 3 files changed, 263 insertions(+), 346 deletions(-) -- 2.49.1
