The maximum pipe BPP value (used as the DSC input BPP) has been aligned already to the corresponding source/sink input BPP capabilities in intel_dp_compute_config_limits(). So it isn't needed to perform the same alignment again in intel_edp_dsc_compute_pipe_bpp() called later, this function can simply use the already aligned maximum pipe BPP value, do that.
Reviewed-by: Vinod Govindapillai <[email protected]> Signed-off-by: Imre Deak <[email protected]> --- drivers/gpu/drm/i915/display/intel_dp.c | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 36cbb6aef2434..e38e307bddfff 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -2338,26 +2338,16 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp, struct drm_connector_state *conn_state, const struct link_config_limits *limits) { - struct intel_display *display = to_intel_display(intel_dp); struct intel_connector *connector = to_intel_connector(conn_state->connector); int pipe_bpp, forced_bpp; forced_bpp = intel_dp_force_dsc_pipe_bpp(intel_dp, limits); - - if (forced_bpp) { + if (forced_bpp) pipe_bpp = forced_bpp; - } else { - int max_bpc = limits->pipe.max_bpp / 3; + else + pipe_bpp = limits->pipe.max_bpp; - /* For eDP use max bpp that can be supported with DSC. */ - pipe_bpp = intel_dp_dsc_compute_max_bpp(connector, max_bpc); - if (!is_dsc_pipe_bpp_sufficient(limits, pipe_bpp)) { - drm_dbg_kms(display->drm, - "Computed BPC is not in DSC BPC limits\n"); - return -EINVAL; - } - } pipe_config->port_clock = limits->max_rate; pipe_config->lane_count = limits->max_lane_count; -- 2.49.1
