Unused bandwidth can be used by external display agents for Panel Replay enabled DP panel during idleness with link on. Enable source to replace dummy data from the display with data from another agent by programming TRANS_DP2_CTL [Panel Replay Tunneling Enable].
v2: - Enable pr bw optimization along with panel replay enable. [Jani] v3: - Write TRANS_DP2_CTL once for both bw optimization and panel replay enable. [Jani] Bspec: 68920 Signed-off-by: Animesh Manna <[email protected]> --- .../gpu/drm/i915/display/intel_display_regs.h | 1 + drivers/gpu/drm/i915/display/intel_psr.c | 26 +++++++++++++++++-- 2 files changed, 25 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h index 9e0d853f4b61..b6fc249a9f09 100644 --- a/drivers/gpu/drm/i915/display/intel_display_regs.h +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h @@ -2051,6 +2051,7 @@ #define TRANS_DP2_CTL(trans) _MMIO_TRANS(trans, _TRANS_DP2_CTL_A, _TRANS_DP2_CTL_B) #define TRANS_DP2_128B132B_CHANNEL_CODING REG_BIT(31) #define TRANS_DP2_PANEL_REPLAY_ENABLE REG_BIT(30) +#define TRANS_DP2_PR_TUNNELING_ENABLE REG_BIT(26) #define TRANS_DP2_DEBUG_ENABLE REG_BIT(23) #define _TRANS_DP2_VFREQHIGH_A 0x600a4 diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c index 91f4ac86c7ad..4283455d58fb 100644 --- a/drivers/gpu/drm/i915/display/intel_psr.c +++ b/drivers/gpu/drm/i915/display/intel_psr.c @@ -44,6 +44,7 @@ #include "intel_dmc.h" #include "intel_dp.h" #include "intel_dp_aux.h" +#include "intel_dp_tunnel.h" #include "intel_dsb.h" #include "intel_frontbuffer.h" #include "intel_hdmi.h" @@ -1018,11 +1019,30 @@ static u8 frames_before_su_entry(struct intel_dp *intel_dp) return frames_before_su_entry; } +static bool intel_psr_allow_pr_bw_optimization(struct intel_dp *intel_dp) +{ + struct intel_display *display = to_intel_display(intel_dp); + u8 val; + + if (DISPLAY_VER(display) < 35) + return false; + + if (!intel_dp_tunnel_bw_alloc_is_enabled(intel_dp)) + return false; + + drm_dp_dpcd_readb(&intel_dp->aux, DP_TUNNELING_CAPABILITIES, &val); + if (!(val & DP_PANEL_REPLAY_OPTIMIZATION_SUPPORT)) + return false; + + return true; +} + static void dg2_activate_panel_replay(struct intel_dp *intel_dp) { struct intel_display *display = to_intel_display(intel_dp); struct intel_psr *psr = &intel_dp->psr; enum transcoder cpu_transcoder = intel_dp->psr.transcoder; + u32 dp2_ctl_val = TRANS_DP2_PANEL_REPLAY_ENABLE; if (intel_dp_is_edp(intel_dp) && psr->sel_update_enabled) { u32 val = psr->su_region_et_enabled ? @@ -1035,12 +1055,14 @@ static void dg2_activate_panel_replay(struct intel_dp *intel_dp) val); } + if (!intel_dp_is_edp(intel_dp) && intel_psr_allow_pr_bw_optimization(intel_dp)) + dp2_ctl_val |= TRANS_DP2_PR_TUNNELING_ENABLE; + intel_de_rmw(display, PSR2_MAN_TRK_CTL(display, intel_dp->psr.transcoder), 0, ADLP_PSR2_MAN_TRK_CTL_SF_CONTINUOS_FULL_FRAME); - intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0, - TRANS_DP2_PANEL_REPLAY_ENABLE); + intel_de_rmw(display, TRANS_DP2_CTL(intel_dp->psr.transcoder), 0, dp2_ctl_val); } static void hsw_activate_psr2(struct intel_dp *intel_dp) -- 2.29.0
