Quoting Suraj Kandpal (2025-12-30 05:31:42-03:00) >Clear the response ready and error bit of PORT_P2M_MESSAGE_BUS_STATUS >before writing the transaction pending bit of >PORT_M2P_MSGBUS_CTL as that is a hard requirement. If not done >we find that the PHY hangs since it ends up in a weird state if left >idle for more than 1 hour.
Since the series title refers to suspend/resume, is there an easy way of reproducing this via some power state transition? I'm wondering if we are looking at a driver issue here or if this is really something else. I see that we usually call intel_cx0_bus_reset() in error paths, which contains a call to intel_clear_response_ready_flag(), but it could end up being not called if the reset times out. Do we see error messages from the driver when the PHY hangs? -- Gustavo Sousa > >Bspec: 65101 >Signed-off-by: Suraj Kandpal <[email protected]> >--- > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 4 ++++ > 1 file changed, 4 insertions(+) > >diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c >b/drivers/gpu/drm/i915/display/intel_cx0_phy.c >index 5edd293b533b..5ebc3404eee2 100644 >--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c >+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c >@@ -222,6 +222,8 @@ static int __intel_cx0_read_once(struct intel_encoder >*encoder, > return -ETIMEDOUT; > } > >+ intel_clear_response_ready_flag(encoder, lane); >+ > intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, > lane), > XELPDP_PORT_M2P_TRANSACTION_PENDING | > XELPDP_PORT_M2P_COMMAND_READ | >@@ -293,6 +295,8 @@ static int __intel_cx0_write_once(struct intel_encoder >*encoder, > return -ETIMEDOUT; > } > >+ intel_clear_response_ready_flag(encoder, lane); >+ > intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, > lane), > XELPDP_PORT_M2P_TRANSACTION_PENDING | > (committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED : >-- >2.34.1 >
