Quoting Bhadane, Dnyaneshwar (2026-01-07 03:31:23-03:00) > > >> -----Original Message----- >> From: Sousa, Gustavo <[email protected]> >> Sent: Wednesday, January 7, 2026 3:10 AM >> To: [email protected]; [email protected] >> Cc: Bhadane, Dnyaneshwar <[email protected]>; Sousa, Gustavo >> <[email protected]> >> Subject: [PATCH v2] drm/i915/cdclk: Incorporate Xe3_LPD changes for CD2X >> divider >> >> On Xe3_LPD, there is no instruction to program the CD2X divider anymore and >> the hardware is expected to always use the default value of 0b00, meaning >> "divide by 1". >> >> With that, the CDCLK_CTL register was changed so that: >> >> (1) The field "CD2X Divider Select" became a debug-only field. >> Because we are programming CDCLK_CTL with a direct write instead >> of read-modify-write operation, we still need to program "CD2X >> Divider Select" in order to keep the field from deviating from its >> default value. Let's, however, throw a warning if we encounter a >> CDCLK value that would result in an unexpected value for that >> field. >> >> (2) The field "CD2X Pipe Select" has been removed. In fact, some >> debugging in a PTL machine showed that such field comes back as >> zero after writing a non-zero value to it. As such, do not >> program it starting with Xe3_LPD. >> >> v2: >> - Add missing "val |= " when calling bxt_cdclk_cd2x_pipe(). >> (Dnyaneshwar) >> >> Bspec: 68864, 69090 >> Cc: Dnyaneshwar Bhadane <[email protected]> >> Signed-off-by: Gustavo Sousa <[email protected]> > >LGTM, Thank you for the update. > >Reviewed-by: Dnyaneshwar Bhadane <[email protected]>
Pushed to drm-intel-next. Thanks for the review! -- Gustavo Sousa
