This is v2 of [1], with the updates on commit messages and fuzzy clock check.
[1] https://lore.kernel.org/intel-xe/[email protected]/ Cc: Suraj Kandpal <[email protected]> Cc: Imre Deak <[email protected]> Mika Kahola (15): drm/i915/cx0: Move C10 port clock calculation drm/i915/cx0: Move C20 port clock calculation drm/i915/cx0: Drop Cx0 crtc_state from HDMI TMDS pll divider calculation drm/i915/lt_phy: Drop LT PHY crtc_state for port calculation drm/i915/cx0: Drop encoder from port clock calculation drm/i915/cx0: Create macro around PLL tables drm/i915/lt_phy: Create macro for LT PHY PLL state drm/i915/display: Add helper function for fuzzy clock check drm/i915/cx0: Fix HDMI FRL clock rates drm/i915/cx0: Add a fuzzy check for DP/HDMI clock rates during programming drm/i915/cx0: Verify C10/C20 pll dividers drm/i915/lt_phy: Add verification for lt phy pll dividers drm/i915/cx0: Drop C20 25.175 MHz rate drm/i915/lt_phy: Drop 27.2 MHz rate drm/i915/display: Remove .clock member from eDP/DP/HDMI pll tables drivers/gpu/drm/i915/display/intel_cx0_phy.c | 727 ++++++++++-------- drivers/gpu/drm/i915/display/intel_cx0_phy.h | 1 + drivers/gpu/drm/i915/display/intel_ddi.c | 4 +- drivers/gpu/drm/i915/display/intel_dpll.c | 8 +- drivers/gpu/drm/i915/display/intel_dpll.h | 1 + drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 11 +- drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 3 - drivers/gpu/drm/i915/display/intel_hdmi.c | 19 +- drivers/gpu/drm/i915/display/intel_lt_phy.c | 239 +++--- drivers/gpu/drm/i915/display/intel_lt_phy.h | 5 +- .../drm/i915/display/intel_snps_hdmi_pll.c | 2 - 11 files changed, 553 insertions(+), 467 deletions(-) -- 2.43.0
