> Subject: [PATCH v3 00/15] drm/i915/pll: Verify pll dividers and remove > redundant .clock member > > This is v2 of [1], with the updates on commit messages and fuzzy clock check. > > [1] https://lore.kernel.org/intel-xe/20251217151955.1690202-1- > [email protected]/ > > Cc: Suraj Kandpal <[email protected]> > Cc: Imre Deak <[email protected]>
Some checkpatch errors are seen in this that can and should be solved. Other Checkpatch warning seem unavoidable. #102: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:2340: + return abs(clock1 - clock2) <= 1;$ -:102: WARNING:LEADING_SPACE: please, no spaces at the start of a line #102: FILE: drivers/gpu/drm/i915/display/intel_dpll.c:2340: + return abs(clock1 - clock2) <= 1;$ total: 1 errors, 1 warnings, 0 checks, 98 lines checked 53143dadc14d drm/i915/cx0: Fix HDMI FRL clock rates 392ebb6424e0 drm/i915/cx0: Add a fuzzy check for DP/HDMI clock rates during programming 0f3fd13cc6a7 drm/i915/cx0: Verify C10/C20 pll dividers -:70: WARNING:LONG_LINE: line length of 108 exceeds 100 columns #70: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:3878: + intel_c10pll_verify_clock(display, pll_params->clock_rate, pll_params->name, pll_params->c10, true); -:77: WARNING:LONG_LINE: line length of 104 exceeds 100 columns #77: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:3885: + intel_c10pll_verify_clock(display, pll_params->clock_rate, pll_params->name, &pll_state, false); -:116: WARNING:LONG_LINE: line length of 108 exceeds 100 columns #116: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:3924: + intel_c20pll_verify_clock(display, pll_params->clock_rate, pll_params->name, pll_params->c20, true); -:124: WARNING:LONG_LINE: line length of 104 exceeds 100 columns #124: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:3932: + intel_c20pll_verify_clock(display, pll_params->clock_rate, pll_params->name, &pll_state, false); total: 0 errors, 4 warnings, 0 checks, 152 lines checked f912da10fb8c drm/i915/lt_phy: Add verification for lt phy pll dividers -:86: WARNING:LONG_LINE: line length of 114 exceeds 100 columns #86: FILE: drivers/gpu/drm/i915/display/intel_lt_phy.c:2377: + intel_lt_phy_pll_verify_clock(display, pll_params->clock_rate, pll_params->name, pll_params->state, true); -:94: WARNING:LONG_LINE: line length of 108 exceeds 100 columns #94: FILE: drivers/gpu/drm/i915/display/intel_lt_phy.c:2385: + intel_lt_phy_pll_verify_clock(display, pll_params->clock_rate, pll_params->name, &pll_state, false); Regards, Suraj Kandpal > > Mika Kahola (15): > drm/i915/cx0: Move C10 port clock calculation > drm/i915/cx0: Move C20 port clock calculation > drm/i915/cx0: Drop Cx0 crtc_state from HDMI TMDS pll divider > calculation > drm/i915/lt_phy: Drop LT PHY crtc_state for port calculation > drm/i915/cx0: Drop encoder from port clock calculation > drm/i915/cx0: Create macro around PLL tables > drm/i915/lt_phy: Create macro for LT PHY PLL state > drm/i915/display: Add helper function for fuzzy clock check > drm/i915/cx0: Fix HDMI FRL clock rates > drm/i915/cx0: Add a fuzzy check for DP/HDMI clock rates during > programming > drm/i915/cx0: Verify C10/C20 pll dividers > drm/i915/lt_phy: Add verification for lt phy pll dividers > drm/i915/cx0: Drop C20 25.175 MHz rate > drm/i915/lt_phy: Drop 27.2 MHz rate > drm/i915/display: Remove .clock member from eDP/DP/HDMI pll tables > > drivers/gpu/drm/i915/display/intel_cx0_phy.c | 727 ++++++++++-------- > drivers/gpu/drm/i915/display/intel_cx0_phy.h | 1 + > drivers/gpu/drm/i915/display/intel_ddi.c | 4 +- > drivers/gpu/drm/i915/display/intel_dpll.c | 8 +- > drivers/gpu/drm/i915/display/intel_dpll.h | 1 + > drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 11 +- > drivers/gpu/drm/i915/display/intel_dpll_mgr.h | 3 - > drivers/gpu/drm/i915/display/intel_hdmi.c | 19 +- > drivers/gpu/drm/i915/display/intel_lt_phy.c | 239 +++--- > drivers/gpu/drm/i915/display/intel_lt_phy.h | 5 +- > .../drm/i915/display/intel_snps_hdmi_pll.c | 2 - > 11 files changed, 553 insertions(+), 467 deletions(-) > > -- > 2.43.0
