HDMI FRL clock rates are incorrectly defined. Fix these
rates.
Signed-off-by: Mika Kahola <[email protected]>
Reviewed-by: Suraj Kandpal <[email protected]>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index 26d3d41d41a7..eda0e176b8be 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -1924,7 +1924,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_594 =
{
};
static const struct intel_c20pll_state mtl_c20_hdmi_300 = {
- .clock = 3000000,
+ .clock = 300000,
.tx = { 0xbe98, /* tx cfg0 */
0x8800, /* tx cfg1 */
0x0000, /* tx cfg2 */
@@ -1949,7 +1949,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_300 =
{
};
static const struct intel_c20pll_state mtl_c20_hdmi_600 = {
- .clock = 6000000,
+ .clock = 600000,
.tx = { 0xbe98, /* tx cfg0 */
0x8800, /* tx cfg1 */
0x0000, /* tx cfg2 */
@@ -1974,7 +1974,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_600 =
{
};
static const struct intel_c20pll_state mtl_c20_hdmi_800 = {
- .clock = 8000000,
+ .clock = 800000,
.tx = { 0xbe98, /* tx cfg0 */
0x8800, /* tx cfg1 */
0x0000, /* tx cfg2 */
@@ -1999,7 +1999,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_800 =
{
};
static const struct intel_c20pll_state mtl_c20_hdmi_1000 = {
- .clock = 10000000,
+ .clock = 1000000,
.tx = { 0xbe98, /* tx cfg0 */
0x8800, /* tx cfg1 */
0x0000, /* tx cfg2 */
@@ -2024,7 +2024,7 @@ static const struct intel_c20pll_state mtl_c20_hdmi_1000
= {
};
static const struct intel_c20pll_state mtl_c20_hdmi_1200 = {
- .clock = 12000000,
+ .clock = 1200000,
.tx = { 0xbe98, /* tx cfg0 */
0x8800, /* tx cfg1 */
0x0000, /* tx cfg2 */
--
2.43.0
