Incorrect clock is connected to DMG registers. Disable DMG Clock gating during display initialization.
WA: 22021451799 Bspec: 69095 Signed-off-by: Suraj Kandpal <[email protected]> Reviewed-by: Nemesa Garg <[email protected]> --- v1 -> v2: -Remove details from comment (Nemesa) -Add details in commit message (Ville) v2 -> v3: -Move the WA to intel_display_wa.c (Ankit) -Remove stray change (Jani) drivers/gpu/drm/i915/display/intel_display_wa.c | 10 +++++++++- drivers/gpu/drm/i915/i915_reg.h | 1 + 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c index 581d943b9bdc..86a6cc45b6ab 100644 --- a/drivers/gpu/drm/i915/display/intel_display_wa.c +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c @@ -32,9 +32,17 @@ static void adlp_display_wa_apply(struct intel_display *display) intel_de_rmw(display, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0); } +static void xe3plpd_display_wa_apply(struct intel_display *display) +{ + /* Wa_22021451799 */ + intel_de_rmw(display, GEN9_CLKGATE_DIS_0, 0, DMG_GATING_DIS); +} + void intel_display_wa_apply(struct intel_display *display) { - if (display->platform.alderlake_p) + if (DISPLAY_VER(display) == 35) + xe3plpd_display_wa_apply(display); + else if (display->platform.alderlake_p) adlp_display_wa_apply(display); else if (DISPLAY_VER(display) == 12) xe_d_display_wa_apply(display); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5bf3b4ab2baa..f928db78a3fa 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -763,6 +763,7 @@ */ #define GEN9_CLKGATE_DIS_0 _MMIO(0x46530) #define DARBF_GATING_DIS REG_BIT(27) +#define DMG_GATING_DIS REG_BIT(21) #define MTL_PIPEDMC_GATING_DIS(pipe) REG_BIT(15 - (pipe)) #define PWM2_GATING_DIS REG_BIT(14) #define PWM1_GATING_DIS REG_BIT(13) -- 2.34.1
