Move DE_IRQ_REGS to display header to make g4x_dp.c free from i915_reg.h dependency. These registers are only used by display and gvt.
v2: Move DE interrupt regs from common to display header (Jani) Signed-off-by: Uma Shankar <[email protected]> --- drivers/gpu/drm/i915/display/g4x_dp.c | 2 +- .../gpu/drm/i915/display/intel_display_regs.h | 16 ++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 15 --------------- 3 files changed, 17 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c index 4cb753177fd8..017c6dd8f9f6 100644 --- a/drivers/gpu/drm/i915/display/g4x_dp.c +++ b/drivers/gpu/drm/i915/display/g4x_dp.c @@ -8,9 +8,9 @@ #include <linux/string_helpers.h> #include <drm/drm_print.h> +#include <drm/intel/intel_gmd_interrupt.h> #include "g4x_dp.h" -#include "i915_reg.h" #include "intel_audio.h" #include "intel_backlight.h" #include "intel_connector.h" diff --git a/drivers/gpu/drm/i915/display/intel_display_regs.h b/drivers/gpu/drm/i915/display/intel_display_regs.h index 40538910cb09..0164dcbb709f 100644 --- a/drivers/gpu/drm/i915/display/intel_display_regs.h +++ b/drivers/gpu/drm/i915/display/intel_display_regs.h @@ -1049,6 +1049,15 @@ #define SWF3(dev_priv, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x72414 + (i) * 4) #define SWF_ILK(i) _MMIO(0x4F000 + (i) * 4) +#define DEISR _MMIO(0x44000) +#define DEIMR _MMIO(0x44004) +#define DEIIR _MMIO(0x44008) +#define DEIER _MMIO(0x4400c) + +#define DE_IRQ_REGS I915_IRQ_REGS(DEIMR, \ + DEIER, \ + DEIIR) + #define DIGITAL_PORT_HOTPLUG_CNTRL _MMIO(0x44030) #define DIGITAL_PORTA_HOTPLUG_ENABLE (1 << 4) #define DIGITAL_PORTA_PULSE_DURATION_2ms (0 << 2) /* pre-HSW */ @@ -1792,6 +1801,13 @@ SDE_TC_HOTPLUG_ICP(HPD_PORT_TC2) | \ SDE_TC_HOTPLUG_ICP(HPD_PORT_TC1)) +/* PCH */ + +#define SDEISR _MMIO(0xc4000) +#define SDEIMR _MMIO(0xc4004) +#define SDEIIR _MMIO(0xc4008) +#define SDEIER _MMIO(0xc400c) + #define SDE_IRQ_REGS I915_IRQ_REGS(SDEIMR, \ SDEIER, \ SDEIIR) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 22b68ddfa7b4..6cb72e6e9086 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -728,15 +728,6 @@ #define VLV_MASTER_IER _MMIO(0x4400c) /* Gunit master IER */ #define MASTER_INTERRUPT_ENABLE (1 << 31) -#define DEISR _MMIO(0x44000) -#define DEIMR _MMIO(0x44004) -#define DEIIR _MMIO(0x44008) -#define DEIER _MMIO(0x4400c) - -#define DE_IRQ_REGS I915_IRQ_REGS(DEIMR, \ - DEIER, \ - DEIIR) - #define GTISR _MMIO(0x44010) #define GTIMR _MMIO(0x44014) #define GTIIR _MMIO(0x44018) @@ -868,12 +859,6 @@ #define GMD_ID_RELEASE_MASK REG_GENMASK(21, 14) #define GMD_ID_STEP REG_GENMASK(5, 0) -/* PCH */ - -#define SDEISR _MMIO(0xc4000) -#define SDEIMR _MMIO(0xc4004) -#define SDEIIR _MMIO(0xc4008) -#define SDEIER _MMIO(0xc400c) /* Icelake PPS_DATA and _ECC DIP Registers. * These are available for transcoders B,C and eDP. -- 2.50.1
