To distinguish the valid 3D LUT settings for Intel platforms with different Display Engine IPs.
Signed-off-by: Austin Hu <[email protected]> --- drivers/gpu/drm/i915/display/intel_color.c | 38 +++++++++++-------- .../drm/i915/display/intel_color_pipeline.c | 6 +-- 2 files changed, 25 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index dff33c9c1..1e89dc006 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -4106,22 +4106,28 @@ static void glk_lut_3d_commit(struct intel_dsb *dsb, } if (enable) { - val = LUT_3D_ENABLE | LUT_3D_READY; - - switch (plane->id) { - case PLANE_1: - val |= LUT_3D_BIND_PLANE_1; - break; - case PLANE_2: - val |= LUT_3D_BIND_PLANE_2; - break; - case PLANE_3: - val |= LUT_3D_BIND_PLANE_3; - break; - default: - /* Attached the 3D LUT block to Pipe. */ - val |= LUT_3D_BIND_PIPE; - break; + val = LUT_3D_ENABLE; + + if (DISPLAY_VER(display) >= 30) { + val |= LUT_3D_READY; + + if (DISPLAY_VER(display) >= 35) { + switch (plane->id) { + case PLANE_1: + val |= LUT_3D_BIND_PLANE_1; + break; + case PLANE_2: + val |= LUT_3D_BIND_PLANE_2; + break; + case PLANE_3: + val |= LUT_3D_BIND_PLANE_3; + break; + default: + /* Attached the 3D LUT block to Pipe. */ + val |= LUT_3D_BIND_PIPE; + break; + } + } } } diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.c b/drivers/gpu/drm/i915/display/intel_color_pipeline.c index d26b0f134..e1bf7990c 100644 --- a/drivers/gpu/drm/i915/display/intel_color_pipeline.c +++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.c @@ -12,6 +12,7 @@ #define MAX_COLOR_PIPELINES 1 #define PLANE_DEGAMMA_SIZE 128 #define PLANE_GAMMA_SIZE 32 +#define DIM_SIZE_3D_LUT 17 static int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct drm_prop_enum_list *list, @@ -47,11 +48,10 @@ int _intel_color_pipeline_plane_init(struct drm_plane *plane, struct drm_prop_en drm_colorop_set_next_property(prev_op, &colorop->base); prev_op = &colorop->base; - if ((DISPLAY_VER(display) >= 15) && HAS_3D_LUT(display) && - intel_color_crtc_has_3dlut(display, pipe)) { + if (HAS_3D_LUT(display) && intel_color_crtc_has_3dlut(display, pipe)) { colorop = intel_colorop_create(INTEL_PLANE_CB_3DLUT); - ret = drm_plane_colorop_3dlut_init(dev, &colorop->base, plane, 17, + ret = drm_plane_colorop_3dlut_init(dev, &colorop->base, plane, DIM_SIZE_3D_LUT, DRM_COLOROP_LUT3D_INTERPOLATION_TETRAHEDRAL, true); if (ret) -- 2.34.1
