If we get the final value of zero as a count of free
entries available, we will underflow our own fifo_count
and then it will take a long time before we check things again.
Admittedly we are in trouble already if we get into this situation,
but prevent the underflow by returning early.
v2: Less convoluted control flow (Daniel Vetter)
v3: Kill redundant loop<0 check (Ville Syrjälä)
Signed-off-by: Mika Kuoppala <mika.kuopp...@intel.com>
---
drivers/gpu/drm/i915/intel_uncore.c | 23 +++++++++++------------
1 file changed, 11 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_uncore.c
b/drivers/gpu/drm/i915/intel_uncore.c
index 76dc185..72f74d0 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -154,10 +154,8 @@ static void __gen7_gt_force_wake_mt_put(struct
drm_i915_private *dev_priv,
gen6_gt_check_fifodbg(dev_priv);
}
-static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
+static bool __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
{
- int ret = 0;
-
/* On VLV, FIFO will be shared by both SW and HW.
* So, we need to read the FREE_ENTRIES everytime */
if (IS_VALLEYVIEW(dev_priv->dev))
@@ -172,13 +170,14 @@ static int __gen6_gt_wait_for_fifo(struct
drm_i915_private *dev_priv)
udelay(10);
fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) &
GT_FIFO_FREE_ENTRIES_MASK;
}
- if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
- ++ret;
+ if (WARN_ON(fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
+ return true;
+
dev_priv->uncore.fifo_count = fifo;
}
dev_priv->uncore.fifo_count--;
- return ret;
+ return false;
}
static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
@@ -642,13 +641,13 @@ gen5_write##x(struct drm_i915_private *dev_priv, off_t
reg, u##x val, bool trace
#define __gen6_write(x) \
static void \
gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool
trace) { \
- u32 __fifo_ret = 0; \
+ bool __fifo_failed = false; \
REG_WRITE_HEADER; \
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
- __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
+ __fifo_failed = __gen6_gt_wait_for_fifo(dev_priv); \
} \
__raw_i915_write##x(dev_priv, reg, val); \
- if (unlikely(__fifo_ret)) { \
+ if (unlikely(__fifo_failed)) { \
gen6_gt_check_fifodbg(dev_priv); \
} \
REG_WRITE_FOOTER; \
@@ -657,14 +656,14 @@ gen6_write##x(struct drm_i915_private *dev_priv, off_t
reg, u##x val, bool trace
#define __hsw_write(x) \
static void \
hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool
trace) { \
- u32 __fifo_ret = 0; \
+ bool __fifo_failed = false; \
REG_WRITE_HEADER; \
if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
- __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
+ __fifo_failed = __gen6_gt_wait_for_fifo(dev_priv); \
} \
hsw_unclaimed_reg_clear(dev_priv, reg); \
__raw_i915_write##x(dev_priv, reg, val); \
- if (unlikely(__fifo_ret)) { \
+ if (unlikely(__fifo_failed)) { \
gen6_gt_check_fifodbg(dev_priv); \
} \
hsw_unclaimed_reg_check(dev_priv, reg); \
--
1.7.9.5
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