On Fri, Apr 25, 2014 at 08:14:32PM +0300, ville.syrj...@linux.intel.com wrote: > From: Ville Syrjälä <ville.syrj...@linux.intel.com> > > The ascii art version of the DPIO diagram gets mangled by docbook, so > we can't use it there. Insted provide another version built using > <table>. > > Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
I guess one could also add the AUX units here as well. But that's still way better than what we currently have. Reviewed-by: Damien Lespiau <damien.lesp...@intel.com> -- Damien > --- > Documentation/DocBook/drm.tmpl | 86 > ++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 86 insertions(+) > > diff --git a/Documentation/DocBook/drm.tmpl b/Documentation/DocBook/drm.tmpl > index e361ccd..bf11fe5 100644 > --- a/Documentation/DocBook/drm.tmpl > +++ b/Documentation/DocBook/drm.tmpl > @@ -2945,6 +2945,92 @@ int num_ioctls;</synopsis> > <sect2> > <title>DPIO</title> > !Pdrivers/gpu/drm/i915/i915_reg.h DPIO > + <table id="dpiox2"> > + <title>Dual channel PHY (VLV/CHV)</title> > + <tgroup cols="8"> > + <colspec colname="c0" /> > + <colspec colname="c1" /> > + <colspec colname="c2" /> > + <colspec colname="c3" /> > + <colspec colname="c4" /> > + <colspec colname="c5" /> > + <colspec colname="c6" /> > + <colspec colname="c7" /> > + <spanspec spanname="ch0" namest="c0" nameend="c3" /> > + <spanspec spanname="ch1" namest="c4" nameend="c7" /> > + <spanspec spanname="ch0pcs01" namest="c0" nameend="c1" /> > + <spanspec spanname="ch0pcs23" namest="c2" nameend="c3" /> > + <spanspec spanname="ch1pcs01" namest="c4" nameend="c5" /> > + <spanspec spanname="ch1pcs23" namest="c6" nameend="c7" /> > + <thead> > + <row> > + <entry spanname="ch0">CH0</entry> > + <entry spanname="ch1">CH1</entry> > + </row> > + </thead> > + <tbody valign="top" align="center"> > + <row> > + <entry spanname="ch0">CMN/PLL/REF</entry> > + <entry spanname="ch1">CMN/PLL/REF</entry> > + </row> > + <row> > + <entry spanname="ch0pcs01">PCS01</entry> > + <entry spanname="ch0pcs23">PCS23</entry> > + <entry spanname="ch1pcs01">PCS01</entry> > + <entry spanname="ch1pcs23">PCS23</entry> > + </row> > + <row> > + <entry>TX0</entry> > + <entry>TX1</entry> > + <entry>TX2</entry> > + <entry>TX3</entry> > + <entry>TX0</entry> > + <entry>TX1</entry> > + <entry>TX2</entry> > + <entry>TX3</entry> > + </row> > + <row> > + <entry spanname="ch0">DDI0</entry> > + <entry spanname="ch1">DDI1</entry> > + </row> > + </tbody> > + </tgroup> > + </table> > + <table id="dpiox1"> > + <title>Single channel PHY (CHV)</title> > + <tgroup cols="4"> > + <colspec colname="c0" /> > + <colspec colname="c1" /> > + <colspec colname="c2" /> > + <colspec colname="c3" /> > + <spanspec spanname="ch0" namest="c0" nameend="c3" /> > + <spanspec spanname="ch0pcs01" namest="c0" nameend="c1" /> > + <spanspec spanname="ch0pcs23" namest="c2" nameend="c3" /> > + <thead> > + <row> > + <entry spanname="ch0">CH0</entry> > + </row> > + </thead> > + <tbody valign="top" align="center"> > + <row> > + <entry spanname="ch0">CMN/PLL/REF</entry> > + </row> > + <row> > + <entry spanname="ch0pcs01">PCS01</entry> > + <entry spanname="ch0pcs23">PCS23</entry> > + </row> > + <row> > + <entry>TX0</entry> > + <entry>TX1</entry> > + <entry>TX2</entry> > + <entry>TX3</entry> > + </row> > + <row> > + <entry spanname="ch0">DDI2</entry> > + </row> > + </tbody> > + </tgroup> > + </table> > </sect2> > </sect1> > > -- > 1.8.3.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
